Stack Pointer Management

• US 6,598,151 B1
• Filed: 10/01/1999
• Issued: 07/22/2003
• Est. Priority Date: 10/06/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jackson, Walter A., Rosenzweig, Jack, Laurenti, Gilbert
• Primary Examiner(s): Ellis, Richard L.
• Assistant Examiner(s): DOLLINGER, TONIA LYNN MEONSKE
• Application Number:
  US09/411,416
• Time in Patent Office: 1,390 Days
• Field of Search: 712/227, 712/202, 712/242, 712/228, 712/209
• US Class Current: 712/228
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/607 number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters for applications thereof, see the relevant places, e.g. G06F7/49, G06F7/5013, G06F7/509, H03M1/00, H03M7/20
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01
• CPC Class Codes: G06F 7/762 having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks G06F7/764 - G06F7/768 take precedence
• CPC Class Codes: G06F 7/764 Masking
• CPC Class Codes: G06F 7/78 for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing

Abstract

A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region (910) is used to pass variables to a subroutine and to hold values representative of a first portion of a program counter (1000). A system stack region (911) is used to hold values representative of a remaining portion of the program counter (1001) and to hold additional context information. The user stack region and the system stack region are managed independently so that software from a prior generation processor can be translated to run on processor (100).

Claims

1. A digital system comprising a microprocessor, wherein the microprocessor comprises:

an instruction buffer unit operable to fetch and decode instructions fetched from an instruction memory;

a data computation unit for executing the instructions decoded by the instruction buffer unit;

a program counter which has a first program counter portion and a remaining program counter portion, the program counter operable to provide an instruction address that is provided to the instruction memory;

a first stack pointer operable to address a first stack region in a data memory for saving a first value representative of the first program counter portion in response to a first instruction being executed by the microprocessor; and

a second stack pointer operable to address a second stack region in the data memory for saving a second value representative of the remaining program counter portion in response to executing said first instruction.

2. The digital system of claim 1, wherein the data computation unit is operable to store a first variable value in the first stack region adjacent to the first program counter value using a first stack pointer relative address relative to the first stack pointer in response to executing a second instruction, such that the first stack pointer relative address is not affected by the second program counter value that is stored in the second stack region.

3. The digital system of claim 2, further comprising an instruction memory connected to the instruction buffer for holding a plurality of instructions and a data memory connected to the data computation unit for holding the first stack region and the second stack region.

4. The digital system of claim 1 being a cellular telephone, further comprising:

an integrated keyboard (12) connected to the processor via a keyboard adapter;

a display (14), connected to the processor via a display adapter;

radio frequency (RF) circuitry (16) connected to the processor; and

an aerial (18) connected to the RF circuitry.

5. A method of operating a digital system, comprising the steps of:

executing a plurality of instructions in a processor core, wherein the instructions are fetched in response to a program counter from an instruction memory associated with the processor core;

forming a first stack region for holding a plurality of data values in a data memory associated with the processor core by maintaining a first stack pointer;

forming a second stack region separate from the first stack region in the data memory for storing a second plurality of data values by maintaining a second stack pointer;

storing a first value representative of a first portion of a program counter in the first stack region in response to a first instruction being executed in the processor core; and

storing a second value representative of a remaining portion of the program counter in the second stack region in response to executing said first instruction.

6. The method of claim 5, further comprising the step of storing a first argument value in the first stack region adjacent to the first program counter value using a first stack pointer relative address relative to the first stack pointer in response to executing a second instruction, such that the first stack pointer relative address is not affected by the second program counter value that is stored in the second stack region.

7. The method of claim 5, further comprising the step of storing a context data value adjacent to the second program counter value using a second stack pointer relative address relative to the second stack pointer in response to executing the second instruction, such that a stack pointer relative address relative to the first stack pointer is not affected by the context data value that is stored in the second stack region.

8. The method according to claim 5, further comprising the step of storing a context data value adjacent to the second program counter value using a second stack pointer relative address relative to the second stack pointer in response to executing an interrupt, such that a stack pointer relative address relative to the first stack pointer is not affected by the context data value that is stored in the second stack region.

9. The method of claim 5, further comprising the steps of:

storing a first argument value in the first stack region adjacent to the first program counter value using a first stack pointer relative address relative to the first stack pointer in response to executing a second instruction, such that the first stack pointer relative address is not affected by the second program counter value that is stored in the second stack region;

storing a context data value adjacent to the second program counter value using a second stack pointer relative address relative to the second stack pointer in response to executing the second instruction, such that a stack pointer relative address relative to the first stack pointer is not affected by the context data value that is stored in the second stack region; and

storing a context data value adjacent to the second program counter value using a second stack pointer relative address relative to the second stack pointer in response to executing an interrupt, such that a stack pointer relative address relative to the first stack pointer is not affected by the context data value that is stored in the second stack region.