Integrated circuit I/O using a high performance bus interface

• US 6,598,171 B1
• Filed: 03/28/1997
• Issued: 07/22/2003
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): BANANKHAH, MAJID A
• Application Number:
  US08/829,459
• Time in Patent Office: 2,307 Days
• Field of Search: 713/400, 713/401, 327/325, 327/326, 327/327, 365/230.02, 365/230.08
• US Class Current: 713/401
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A synchronous memory device including at least one memory section having a plurality of memory cells, the memory device comprising:

a clock buffer to receive a first external lock signal and to generate a buffered clock signal;

a first variable delay line, coupled to the clock buffer, to receive the buffered clock signal and provide a first delayed clock signal having a variable delay with respect to the first external clock signal; and

a first delay adjustment circuit, coupled to the first variable delay line, to control the variable delay of the first delayed clock signal based on a timing relationship between the first external clock signal and the first delayed clock signal.

2. The memory device of claim 1, wherein the timing relationship is derived by comparing a clock edge of the first delayed clock signal and a clock edge of the first external clock signal.

3. The memory device of claim 2, wherein the clock edge of the first delayed clock signal is a falling edge and the clock edge of the first external clock signal is a falling edge.

4. The memory device of claim 1, wherein the first delay adjustment circuit includes a receiver circuit to receive the first external clock signal and a feedback clock signal derived from the first delayed clock signal, wherein the receiver circuit provides a output signal to the first variable delay line to control the variable delay of the first delayed clock signal.

5. The memory device of claim 4, wherein the output signal controls the variable delay of the first delayed clock signal such that the receiver circuit samples the first external clock signal in response to transitions of the feedback clock signal.

6. The memory device of claim 4, wherein the receiver circuit includes a filter.

7. The memory device of claim 1, wherein the clock buffer is an amplifier, wherein the first external clock signal exhibits a first voltage swing and the buffered clock signal exhibits a second voltage swing, wherein the second voltage swing is greater than the first voltage swing.

8. The memory device of claim 1, further including a delay line, coupled to the first variable delay line, to receive the first delayed clock signal and induce a fixed delay upon the first delayed clock signal to produce a feedback clock signal, wherein the timing relationship between the first external clock signal and the first delayed clock signal is based on sampling the first external clock signal it response to transitions of the feedback clock signal.

9. The memory device of claim 1, further including:

a second variable delay line, coupled to the first variable delay line, to provide a second delayed clock signal having a variable delay with respect to the first delayed clock signal; and

a second delay adjustment circuit, coupled to the second variable delay line, to control the variable delay of the second delayed clock signal based on a timing relationship between a second external clock signal and the second delayed clock signal.

10. The memory device of claim 9, wherein the variable delay of the second delayed clock signal is controlled such that the second external clock signal is sampled in response to transitions of the second delayed clock signal.

11. The memory device of claim 9, wherein the second external clock signal is a delayed version of the first external clock signal derived by propagating the first external clock signal along a length of external signal trace.

12. The memory device of claim 9, wherein the second delay adjustment circuit includes a receiver circuit to receive the second external clock signal and the second delayed clock signal, wherein the receiver circuit provides an output signal to the second variable delay line to control the variable delay of the second delayed clock signal.

13. The memory device of claim 12, wherein the output signal controls the variable delay of the second delayed clock signal such that the receiver circuit samples the second external clock signal in response to transitions of the second delayed clock signal.

14. The memory device of claim 12, wherein the receiver circuit includes a filter.

15. The memory device of claim 9, further including a third variable delay line, coupled to the first variable delay line, to provide a third delayed clock signal having a variable delay with respect to the first delayed clock signal, wherein the variable delay of the third delayed clock signal is controlled to be half of the variable delay of the second delayed clock signal.

16. The memory device of claim 1, further including:

a second variable delay line to provide a second delayed clock signal, wherein the second delayed clock signal includes a variable delay with respect to the first external clock signal; and

a second delay adjustment circuit, coupled to the second variable delay line, to control the variable delay of the second delayed clock signal based on a timing relationship between the first external clock signal and the second delayed clock signal.

17. The memory device of claim 16, wherein the first delayed clock signal is used to generate a first internal clock signal and the second delayed clock signal is used to generate a second internal clock signal that is complementary to the first internal clock signal, wherein the memory device uses the first internal clock signal to output data during odd bus cycles and the memory device uses the second internal clock signal to output data during even bus cycles.

18. The memory device of claim 16, wherein the timing relationship between the first external clock signal and the second delayed clock signal is derived by comparing a clock edge of the second delayed clock signal and a clock edge of the first external clock signal.

19. The memory device of claim 16, further including:

a third variable delay line, coupled to the second variable delay line, to provide a third delayed clock signal having a variable delay with respect to the second delayed clock signal; and

a third delay adjustment circuit, coupled to the third variable delay line, to control the variable delay of the third delayed clock signal based on a timing relationship between the second external clock signal and the third delayed clock signal.

20. The memory device of claim 1, further including:

input receivers to sample an operation code, wherein the operation code specifies a read operation;

output drivers to output data in response to the operation code specifying the read operation, wherein the data is output using an internal clock signal generated from the first delayed clock signal, wherein;

the output drivers output first data during an odd cycle of the internal clock signal; and

the output drivers output second data during an even cycle of the internal clock signal.