Monitoring error conditions in an integrated circuit

• US 6,598,177 B1
• Filed: 10/01/1999
• Issued: 07/22/2003
• Est. Priority Date: 10/01/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Barnes, William B., Jones, Andrew M.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): DUNCAN, MARC M
• Application Number:
  US09/411,798
• Time in Patent Office: 1,390 Days
• Field of Search: 714/30, 714/43, 714/48, 714/49, 714/53, 714/56
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544

Abstract

The invention relates to monitoring error conditions in an integrated circuit. The integrated circuit has a packet router to which a plurality of functional modules are connected between which packets are transmitted. Each functional module is associated with an error monitoring register for monitoring error conditions. The error monitoring register contains a plurality of error flags which can be set when a particular error condition is detected. The invention particularly but not exclusively relates to the setting of communication error flags relating to errors in communication of the packet.

Claims

1. A integrated circuit comprising:

plurality of functional modules interconnected via an on-chip communication path, each functional module having packet handling circuitry for generating and receiving packets conveyed by the communication path,

wherein each functional module is associated with an error monitoring register for monitoring error conditions and wherein the packet handling circuitry includes error detection logic for detecting an error condition and flagging the error condition in the error monitoring register.

2. An integrated circuit according to claim 1, wherein each error monitoring register contains a set of communication error flags, each of which can be set by said error detection logic.

3. An integrated circuit according to claim 1, wherein the packets conveyed by the communication path include memory access request packets and response packets.

4. An integrated circuit according to claim 3, wherein the packet handling circuitry is operable to generate ordinary response packets in the case that a valid memory access request has been received, and error response packets in the case that an invalid memory access request has been received.

5. An integrated circuit according to claim 4, wherein the error detection logic includes means for detecting that an error response packet has been received and means for setting an error response received communication error flag in the error monitoring register.

6. An integrated circuit according to claim 4, wherein the error detection logic comprises means for detecting that an error response packet has been generated, and means for setting an error response sent communication error flag in the error monitoring register.

7. An integrated circuit according to claim 3, wherein each of said error condition flags can be read or written by said memory access request packets.

8. An integrated circuit according to claim 3, wherein the error detection logic comprises means for monitoring the receipt of request packets and means for setting one or more communication error flags in the error monitoring register if errors are detected in the request packets.

9. An integrated circuit according to claim 3, wherein the error detection logic comprises means for determining that an unsolicited response packet has been received at a functional module and means for setting an unsolicited response communication error flag in the error monitoring register.

10. An integrated circuit according to claim 1, wherein the error monitoring registers form part of a common memory space for the integrated circuit, said memory space including a plurality of control blocks associated respectively with the functional modules.

11. An integrated circuit according to claim 10, wherein each control block comprises a plurality of control registers, including said error monitoring register implemented as memory at the respective functional block.

12. An integrated circuit according to claim 1, wherein one of said functional modules provides an off-chip communication link connectable to a host computer.

13. A computer system comprising an integrated circuit according to claim 1 and a host computer connected to the integrated circuit via an off-chip link provided by one of said functional modules, said host computer being operable to execute a diagnostic routine, wherein each error monitoring register is responsive to a read request from the host computer to return the condition of the error flags for diagnostic purposes.

14. A functional module having an interface for connection to a packet router, the functional module having packet handling circuitry for generating and receiving packets conveyed by the packet router across said interface, wherein the packet handling circuitry includes error detection logic for detecting an error condition in packets conveyed by the packet router and setting one or more of a set of communication error flags in an error monitoring register implemented at the functional module.

15. A functional module according to claim 14, wherein the packet handling circuitry includes means for generating memory access request packets.

16. A functional module according to claim 15, wherein the packet handling circuitry comprises means for generating ordinary response packets when a valid memory access request is received and error response packets when an invalid memory access request is received, said response packets being directed to a source of the memory access request packets via the packet router.

17. A functional module according to claim 16, wherein the error detection logic comprises means for setting a first communication error flag to denote that an error response has been generated.

18. A functional module according to claim 16, wherein the error detection logic comprises means for setting a second communication error flag in the case that an error response packet has been received.

19. A functional module according to claim 16, wherein the error detection logic comprises means for monitoring the receipt of an unsolicited response packet and means for setting a third communication error flag if that condition is detected.

20. A functional module according to claim 15, wherein the error detection logic comprises means for monitoring memory access request packets and means for setting one or more communication error flags in the case that errors exist in said request packets.

21. A method of monitoring errors arising in the transmission of packets conveyed by a packet router interconnecting a plurality of functional modules wherein each functional module has packet handling circuitry for generating and receiving packets, the method comprising:

at each functional module, monitoring the receipt of packets conveyed by the packet router to that functional module;

determining the nature of the received packet amongst the group of packet types including a memory access request packet, an ordinary response packet and an error response packet; and

in the case of receipt of an error response packet, setting a communication error flag at the functional module to denote that an error response packet has been received.