Peripheral breakpoint signaler

• US 6,598,178 B1
• Filed: 06/01/1999
• Issued: 07/22/2003
• Est. Priority Date: 06/01/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Ma, Zhigang, Yee, Oceager P.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): CHU, GABRIEL L
• Application Number:
  US09/322,920
• Time in Patent Office: 1,512 Days
• Field of Search: 714/34, 714/44, 714/25, 714/32, 714/28, 703/28, 710/103
• US Class Current: 714/34
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects

Abstract

The present invention provides an architecture for a peripheral device to activate a breakpoint in a processor or other device under emulation. A peripheral breakpoint active signaler allows the peripheral to signal the occurrence of a breakpoint to the processor using a halt or trap line to the processor. This invention provides developers with increased code development capabilities by allowing them to set breakpoints in a peripheral device for the benefit of a processor interfaced with the peripheral to detect when a certain external event has occurred based on the perspective of a peripheral. A breakpoint control register individually enables breakpointing capability of each peripheral with respect to having the capability to halt the processor. Each peripheral has the capability to output a breakpoint request signal to set a bit in a breakpoint status register for readback by the processor, through an external port such as a JTAG test port, or other device.

Claims

1. A device to initiate and then synchronize a breakpoint from a peripheral to a processor, said device comprising:

a peripheral generating a breakpoint signal based on a user defined event for said peripheral; and

a circuit to process said breakpoint signal, independent of information passed on busses associated with a processor, to activate a halt input of said processor, said circuit comprising a control register adapted to enable said peripheral generating said breakpoint signal.

2. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 1, wherein:

said control register enables said peripheral by setting a register bit assigned to said peripheral.

3. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 1, wherein:

said control register is programmable by one of said processor and a development port.

4. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 1, wherein said circuit further comprises:

a status register adapted to monitor said peripheral generating said breakpoint signal.

5. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 4, wherein:

said status register provides data to one of said processor and a development port.

6. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 4 wherein:

said status register monitors said peripheral by assigning a register bit to said peripheral.

7. The device to initiate and then synchronize a breakpoint from a peripheral to a processor according to claim 1, wherein said circuit further comprises:

an OR gate, an output of said OR gate interfacing to said halt input of said processor, and inputs to said OR gate are based on said breakpoint signal and a breakpoint halt signal from a breakpoint monitor associated with said processor.

8. A method for synchronizing a breakpoint, said method comprising:

generating a breakpoint signal in a peripheral based on a user defined event;

activating a halt input of a processor associated with said peripheral, said activation being independent of information passed on busses associated with said processor; and

controlling said peripheral generating said breakpoint signal using a control register.

9. The method according to claim 8, said method further comprising:

assigning a register bit in said control register to said peripheral.

10. The method according to claim 8, said method further comprising:

programming said control register from one of said processor and a development port.

11. The method according to claim 8, said method further comprising:

monitoring said peripheral generating said breakpoint signal with a status register.

12. The method according to claim 11, said method further comprising:

interfacing said status register with one of said processor and a development port.

13. The method according to claim 11, said method further comprising:

assigning a register bit in said status register to said peripheral.

14. The method according to claim 8, said method further comprising:

interfacing an output of an OR gate to said halt input of said processor, said OR gate having inputs corresponding to said breakpoint signal and a breakpoint halt signal from a breakpoint monitor associated with said processor.

15. An apparatus for synchronizing a breakpoint, said apparatus comprising:

a peripheral generating a breakpoint signal dependent on a user defined event for said peripheral; and

a hardware development block associated with testing and debugging of a processor wherein said hardware development block processes said breakpoint signal to activate a halt input of said processor independent of information passed on busses associated with said processor, said hardware development block interfacing with a serial test port including a JTAG port.

16. The apparatus according to claim 15, wherein:

said serial test port includes a scan chain control register adapted to enable said peripheral generating said breakpoint signal.

17. The apparatus according to claim 16, wherein:

said scan control register enables said peripheral by setting a register bit assigned to said peripheral.

18. The apparatus according to claim 15, further comprising:

a status register adapted to monitor said peripheral generating said breakpoint signal.

19. The apparatus according to claim 18, wherein:

said status register interfaces to one of said processor and a serial test port.