Method of forming shallow trench isolation for thin silicon-on-insulator substrates

• US 6,599,813 B2
• Filed: 06/29/2001
• Issued: 07/29/2003
• Est. Priority Date: 06/29/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schepis, Dominic, Beyer, Klaus
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Luu, Chuong A
• Application Number:
  US09/895,680
• Publication Number:
  US 20030003678A1
• Time in Patent Office: 760 Days
• Field of Search: 438/588, 438/404, 438/424, 438/692, 438/259, 438/155, 438/425, 438/426, 438/427
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence

Abstract

A method is disclosed for forming shallow trench isolation (STI) on a thin silicon-on-insulator (SOI) substrate. The method comprises depositing a first polysilicon layer; depositing a polish stop layer on the first polysilicon layer; forming a plurality of trenches in the substrate; filling the trenches with silicon oxide; CMP polishing a first portion of the silicon oxide layer down to the polish stop layer; etching a second portion of the silicon oxide layer down to below the polish stop layer and above the first polysilicon layer; removing the polish stop layer; depositing a second polysilicon layer; and forming a polysilicon gate comprised of the first and second polysilicon layers. Well ion implants may be performed prior to gate formation, thereby preventing exposure of STI oxide to sacrificial oxide growth and removal, eliminating excessive recess in STI structures. STI oxide seam leakage due to polysilicon sidewalls remaining after polysilicon gate etch are also avoided.

Claims

1. A method for forming shallow trench isolation on a silicon-on-insulator (SOI) substrate for isolating device areas on said SOI substrate, wherein said SOI substrate comprises a silicon layer on top of a buried oxide layer, the method comprising the steps of:

forming a gate oxide layer on said silicon layer;

depositing a first polysilicon layer on said gate oxide layer;

depositing a polish stop layer on said first polysilicon layer;

forming a plurality of trenches, wherein said trenches have a depth extending through said polish stop layer, said first polysilicon layer, said gate oxide layer, and said silicon layer;

conformally depositing a silicon oxide layer in said trenches and on said polish stop layer;

removing a first portion of said silicon oxide layer by chemical mechanical polishing, such that the top surface of said silicon oxide layer in said trenches is polished down to the same height as the top surface of said polish stop layer;

removing a second portion of said silicon oxide layer by etching, such that the top surface of said silicon oxide layer is etched down to a height below the top surface of said polish stop layer and above the top surface of said first polysilicon layer;

removing said polish stop layer;

depositing a second polysilicon layer on said silicon oxide layer and said first polysilicon layer; and

forming a polysilicon gate comprised of said first and second polysilicon layers by photolithography masking and etching said first and second polysilicon layers.

2. The method of claim 1 wherein said silicon layer has a thickness of less than about 1000 Å

.

3. The method of claim 1 wherein said silicon layer has a thickness of less than about 500 Å

.

4. The method of claim 1 wherein said gate oxide layer is formed by thermal oxidation in an atmosphere comprising a gas selected from the group consisting of oxygen and nitrous oxide.

5. The method of claim 1 wherein said gate oxide layer has a thickness of about 10 Å

to about 30 Å

.

6. The method of claim 1 wherein said first polysilicon layer is deposited by low pressure chemical vapor deposition using silane.

7. The method of claim 1 wherein said first polysilicon layer has a thickness of about 300 Å

to about 600 Å

.

8. The method of claim 1 wherein said first polysilicon layer has a thickness of about 500 Å

.

9. The method of claim 1 wherein said polish stop layer comprises silicon nitride.

10. The method of claim 1 wherein said polish stop layer is deposited by low pressure chemical vapor deposition using silane and ammonia.

11. The method of claim 1 wherein said polish stop layer has a thickness of about 500 Å

to about 1000 Å

.

12. The method of claim 1 wherein said polish stop layer has a thickness of about 800 Å

.

13. The method of claim 1 wherein said trenches are formed by photolithography masking and anisotropic etching.

14. The method of claim 13 wherein said anisotropic etching comprises directional reactive ion etching.

15. The method of claim 1 wherein said trenches have a depth of about 1700 Å

to about 2200 Å

.

16. The method of claim 1 further comprising forming an oxide liner in said trenches prior to depositing said silicon oxide layer.

17. The method of claim 16 wherein said oxide liner is formed by thermal oxidation in an oxygen atmosphere.

18. The method of claim 16 wherein said oxide liner has a thickness of about 50 Å

to about 300 Å

.

19. The method of claim 16 wherein said oxide liner has a thickness of about 100 Å

.

20. The method of claim 1 wherein said silicon oxide layer is deposited by a high density plasma process.

21. The method of claim 1 wherein said silicon oxide layer is deposited by low pressure chemical vapor deposition using tetraethylorthosilicate oxide.

22. The method of claim 1 wherein said silicon oxide layer has a thickness greater than said trench depth.

23. The method of claim 1 wherein said silicon oxide layer has a thickness of about 1800 Å

to about 2400 Å

.

24. The method of claim 1 wherein said first portion of said silicon oxide layer is removed by chemical mechanical polishing using a slurry comprising cerium oxide and a surfactant.

25. The method of claim 1 wherein said second portion of said silicon oxide layer is removed by a wet etching process.

26. The method of claim 1 wherein said second portion of said silicon oxide layer is removed by a reactive ion etching process.

27. The method of claim 1 wherein said second portion of said silicon oxide layer is removed such that the top surface of said silicon oxide layer is at least about 200 Å

higher than the top surface of said silicon layer, and the top surface of said silicon oxide layer is no more than about 200 Å

higher than the top surface of said first polysilicon layer.

28. The method of claim 1 wherein said polish stop layer is removed by a selective reactive ion etching process.

29. The method of claim 1 wherein said second polysilicon layer is deposited by low pressure chemical vapor deposition using silane.

30. The method of claim 1 wherein said second polysilicon layer has a thickness of about 750 Å

to about 1500 Å

.

31. The method of claim 1 wherein said second polysilicon layer has a thickness of about 1000 Å

.

32. The method of claim 1 further comprising the step of depositing an oxide layer on said second polysilicon layer prior to forming said polysilicon gate.

33. The method of claim 32 wherein said oxide layer is deposited by plasma-enhanced low pressure chemical vapor deposition.

34. The method of claim 32 wherein said oxide layer has a thickness of about 500 Å

.

35. The method of claim 1 wherein said polysilicon gate is formed by photolithography masking and reactive ion etching.

36. The method of claims 1 further comprising, prior to forming said gate oxide layer on said silicon layer, the steps of:

forming a sacrificial oxide layer on said silicon layer;

performing threshold ion implantations and source/drain well implantations through said sacrificial oxide layer; and

removing said sacrificial oxide layer.