Low temperature semiconductor layering and three-dimensional electronic circuits using the layering

• US 6,600,173 B2
• Filed: 08/30/2001
• Issued: 07/29/2003
• Est. Priority Date: 08/30/2000
• Status: Expired due to Fees

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Tiwari, Sandip
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/943,099
• Publication Number:
  US 20020025604A1
• Time in Patent Office: 698 Days
• Field of Search: 438/118, 438/458, 438/484, 257/74, 257/347, 257/758
• US Class Current: 257/74
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 977/712 formed from plural layers of nanosized material, e.g. stacked structures
• CPC Class Codes: Y10S 977/896 Chemical synthesis, e.g. chemical bonding or breaking
• CPC Class Codes: Y10S 977/936 in a transistor or 3-terminal device

Abstract

In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded together to form a bonded structure that is heated until a portion of the donor substrate exfoliates from the bonded structure and leaves a residual portion of the donor bonded to the receiver. To form three dimensional interconnected integrated circuits from devices formed on donor and receiver substrates, the receiver devices are covered with a protective and bonding layer. Interconnect structures extending from the surface of the protective and bonding layer to the devices of the receiver are formed, and a donor is implanted with two or more exfoliating implants. After bonding and heating of the two substrates until a portion of the donor exfoliates from the bonded substrates, leaving a remaining layer of the donor bonded to the receiver, the resulting devices are interconnected in an integrated circuit.

Claims

1. A method for forming a three dimensional interconnected structure comprising the steps of:

forming sets of devices on at least one receiver substrate of semiconductor material and at least one donor substrate of semiconductor material;

implanting said at least one donor substrate of semiconductor material with two or more exfoliating implants;

bonding said at least one donor substrate to said at least one receiver substrate to form a bonded structure; and

heating the bonded structure until a portion of said at least one donor substrate exfoliates from the bonded structure and leaves a residual portion of said at least one donor substrate bonded to said at least one receiver substrate.

2. The method of claim 1 comprising the further steps of cleaning, polishing, and oxidizing a surface of said residual portion of donor substrate.

3. The method of claim 2 wherein said oxidizing step is carried out during a low temperature isothermic process or during a rapid thermal annealing process.

4. The method of claim 2 wherein said oxidizing step oxidizes an exfoliated surface of said residual portion of donor substrate and an other, subcutaneous surface of said at least one donor substrate.

5. The method of claim 2 wherein said donor semiconductor and said receiver semiconductor are silicon, further comprising the step of stripping an oxide from an exfoliated surface of the donor substrate to form a silicon on insulator structure.

6. The method of claim 1 further comprising the step of oxidizing the surface of receiver substrate before bonding the donor substrate to the receiver substrate.

7. The method of claim 1 further comprising the step of interconnecting devices on the receiver substrate with devices on the donor substrate.

8. The method of claim 7 further comprising the step of generating implant ions from materials that form a gas at low temperatures.

9. The method of claim 8 wherein the gases that form low temperature gases are selected from the group consisting of hydrogen, helium, neon and argon.

10. The method of claim 1 further comprising the step of covering a donor device with a protective wafer before implanting.

11. The method of claim 10 further comprising step of covering the receiver substrate with a protective wafer prior to bonding.

12. The method of claim 1 further comprising the steps of forming an insulating layer between the two substrates and forming an interconnect structure in the insulating layer for connection devices on one substrate to devices on the other substrate.

13. The method of claim 12 wherein said interconnect structures in the insulating layer comprise doped polysilicon or refractory conductive material.

14. The method of claim 13 wherein said refractory conductive material comprises of one or more materials selected from the group consisting of tungsten, TiN, TaN, ZrN, and WN.

15. The method of claim 1 wherein said three dimensional interconnected structure is a nanomachine device.

16. A method for forming three dimensional interconnected integrated circuits comprising the steps of:

forming devices on donor and receiver substrates;

covering the devices on said receiver substrate with a protective and bonding layer;

forming interconnect structures extending from a surface of the protective and bonding layer to the devices of the receiver substrate;

implanting said donor substrate with two or more exfoliating implants;

bonding said donor substrate and said receiver substrate together;

heating the bonded substrates until a portion of said donor substrate exfoliates from said bonded substrates and leaves a remaining layer of said donor substrate bonded to said receiver substrate; and

interconnecting devices on said receiver substrate and said donor substrate.

17. The method of claim 16 wherein the bonded substrate is annealed at a temperature between 200°

C.-250°

C. for 1 to 48 hours.

18. The method of claim 17 wherein the implant dose is less than 3×

10¹⁶ cm<sup>−

2</sup> and the exfoliation temperature is less than 600°

C.

19. The method of claim 16 wherein the exfoliating implants are derived from gases that are insoluble in donor substrate and have a gaseous phase at low temperatures.

20. The method of claim 16 wherein the exfoliating implants are selected from the group consisting of hydrogen, helium, neon, and argon.

21. The method of claim 16 wherein one or more subsequent donor substrates carrying devices are implanted with exfoliating implants and each subsequent donor substrate is bonded to the most recently bonded donor layer and portions of the subsequent donor substrates not implanted with exfoliating implants are exfoliated from the bonded substrates.

22. The method of claim 16 wherein said donor substrates and said receiver substrates are bonded to each other.

23. The method of claim 16 comprising the further step of polishing an exfoliated surface of the donor substrate and oxidizing the donor substrate.

24. The method of claim 23 wherein said oxidizing of said donor substrate is accomplished during isothermal or rapid thermal processing to improve interface density of said donor substrate.

25. The method of claim 16 wherein an interconnect structure, interconnecting devices on said receiver substrate and said donor substrate, comprises a refractory metal.

26. The method of claim 25 wherein the refractory metal comprises tungsten.

27. A silicon-on-insulator (SOI) integrated circuit comprising;

a receiver substrate of semiconductor material with a first set of devices;

an insulating layer over the receiver substrate;

and an initial exfoliated substrate of semiconductor material over the insulating layer, said initial exfoliated substrate comprising a second set of devices; and

a plurality of conductive interconnections extending from a plurality of device regions in the receiver substrate through the insulating layer and to a plurality of device regions in the donor substrate.

28. The SOI integrated circuit of claim 27 further comprising one or more subsequent exfoliated substrates of semiconductor material sequentially bonded to the initial exfoliated substrate, wherein each exfoliated subsequent substrate comprises one or more devices and each exfoliated subsequent substrate is isolated from adjacent exfoliated substrates by an insulating layer and interconnections extend between adjacent exfoliated substrates and through the intervening insulating layer disposed between the adjacent exfoliated substrates.

29. The SOI of claim 27 wherein the interconnections comprise doped polysilicon or a refractory material isolated from each other in insulating material.

30. The SOI of claim 29 wherein the refractory material is selected from the group consisting of tungsten, TiN, TaN, ZrN and WN, and combinations and alloys thereof.

31. The SOI of claim 28 wherein the interconnections are either plug structures directly connecting devices on a plurality of adjacent wafers substrates or a plurality of planarized structures.

32. An integrated circuit comprising a receiver substrate with a first set of devices;

an insulating layer over the receiver substrate, and at least one exfoliated substrate on the insulating layer, a second set of devices formed in a second, exfoliated substrate, and a plurality of conductive interconnections extending from a plurality of device regions in the receiver substrate to a plurality of device regions in the donor substrate.

33. The integrated circuit of claim 32 wherein the insulating layer comprises a plurality of vias including a conductive material for connecting a device region from a device in the first set of devices to a device region in a device in the second set of devices.

34. The integrated circuit of claim 33 wherein said plurality of device regions of the receiver substrate interconnected with corresponding said plurality of device regions of the donor substrate are in vertical alignment.

35. The integrated circuit of claim 33 wherein said vias extend through the donor substrate.

36. The integrated circuit of claim 33 wherein said vias terminate at a surface of the insulating layer and directly contact the lower surface of corresponding interconnect regions in the donor substrate.

37. The integrated circuit of claim 32 wherein the integrated circuit comprises a device selected from the group consisting of SRAMs, DRAMs, ASICs, logic devices, linear devices, microprocessors and digital signal processors.

38. The integrated circuit of claim 32 wherein a semiconductor material for said donor substrate and said receiver substrate is one selected from the group of Si, Ge, SiGe, and group III-V compounds.