Semiconductor device, method of manufacturing the same and exposure mask for implantation

• US 6,600,180 B1
• Filed: 07/12/2000
• Issued: 07/29/2003
• Est. Priority Date: 01/19/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ueno, Syuuichi, Yamashita, Tomohiro, Sayama, Hirokazu
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Sefer, Ahmed N.
• Application Number:
  US09/614,730
• Time in Patent Office: 1,112 Days
• Field of Search: 257/202-206, 257/296-300, 257/368, 257/797
• US Class Current: 257/206
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A semiconductor device suppressing increase of the number of types of exposure mask for implantations, preventing complication of manufacturing steps and suppressing the manufacturing cost and manufacturing steps therefor are provided. An impurity implantation region (R81) is formed by first implantation with an exposure mask for implantation having an opening at the lower right and this exposure mask for implantation is turned over for forming another impurity implantation region (R82) by second implantation, thereby forming three types of impurity implantation regions including the impurity implantation region (R81) formed through the first implantation, the impurity implantation region (R82) formed through the second implantation and still another impurity implantation region (R83) formed through the first implantation and the second implantation. Four types of regions inclusive of a region (R84) not subjected to impurity implantation can be formed with a single type of exposure mask for implantation. Such implantation regions can be formed also by rotating the exposure mask for implantation.

Claims

1. A semiconductor device at least comprising:

a first impurity region of a first impurity concentration having a first pattern formed in a target layer;

a second impurity region of a second impurity concentration formed in said target layer; and

a third impurity region having a third impurity concentration corresponding to the total of said first and second impurity concentrations formed in said target layer,

wherein said first pattern and said second pattern are identical plane patterns or plane patterns having a turnover relationship with each other.

2. The semiconductor device according to claim 1, wherein

said first and second patterns are rotation-symmetrical.

3. The semiconductor device according to claim 1, wherein

said first and second patterns are line-symmetrical.

4. The semiconductor device according to claim 1, wherein

said first and second impurity concentrations are different from each other.

5. The semiconductor device according to claim 1, wherein

said first and second impurity concentrations are identical to each other.

6. An exposure mask for implantation employed for manufacturing the semiconductor device according to claim 1, used in a first or second arrangement state to satisfy the symmetry between said first and second patterns,

for forming a pattern for implanting an impurity into said target layer corresponding to said first impurity region and said third impurity region when used in said first arrangement state and implanting an impurity into said target layer in regions corresponding to said second impurity region and said third impurity region when used in said second arrangement state.

7. A semiconductor device at least comprising:

a plurality of first impurity regions of a first impurity concentration having predetermined patterns formed in a target layer; and

a symmetrical second impurity region having a second impurity concentration integral times said first impurity concentration formed in said target layer, wherein

respective said predetermined patterns of said plurality of first impurity regions are formed in symmetry.

8. The semiconductor device according to claim 7, wherein

each of said predetermined patterns of said plurality of first impurity regions is rotation-symmetrical.

9. The semiconductor device according to claim 7, wherein