EEPROM with a neutralized doping at tunnel window edge

• US 6,600,188 B1
• Filed: 02/26/2002
• Issued: 07/29/2003
• Est. Priority Date: 06/25/2001
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Jiang, Chun, Mehta, Sunil D.
• Primary Examiner(s): Nhu, David
• Application Number:
  US10/083,728
• Time in Patent Office: 518 Days
• Field of Search: 257/296, 257/314, 257/315, 257/322, 257/336, 257/344, 257/376, 257/549, 257/550
• US Class Current: 257/296
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the programming operation, the P-type lightly-doped drain regions are in contacting with the polysilicon edges. As a result, there is reduced or suppressed the tunneling current to the program junction region so as to improve the efficiency of programming.

Claims

1. A tunnel diode of an EEPROM memory cell, comprising:

a PRJ (program junction) region formed within a semiconductor substrate;

a tunnel layer formed on said PRJ region;

a floating gate electrode formed over said tunnel layer;

a lightly doped region comprised of a first dopant of a first conductivity type formed within said PRJ region on a side of said floating gate electrode;

a highly doped region comprised of a second dopant of a second conductivity type formed within said PRJ region, wherein said highly doped region is formed to contact a side of said lightly doped region further away from said floating gate electrode;

and wherein said first conductivity type of said lightly doped region is opposite to said second conductivity type of said highly doped region.

2. The tunnel diode of claim 1, wherein said lightly doped region is formed when said first dopant is implanted into exposed regions of said PRJ region, with said gate electrode acting as a mask.

3. The tunnel diode of claim 2, further comprising:

a sidewall spacer formed at said side of said gate electrode;

wherein said highly doped region is formed when said second dopant is implanted into exposed regions of said PRJ region, with said gate electrode and said sidewall spacer acting as a mask.

4. The tunnel diode of claim 1, wherein said first conductivity type of said first dopant for forming said lightly doped region is of P-type conductivity, and wherein said second conductivity type of said second dopant for forming said highly doped region is of N-type conductivity.

5. The tunnel diode of claim 1, wherein said tunnel layer is comprised of oxide, and wherein said floating gate electrode is comprised of polysilicon.

6. An EEPROM memory cell comprising:

a read transistor and a sense transistor having drains coupled together to form an output of said EEPROM memory cell and having gates coupled together to form a floating gate node;

a write transistor; and

a tunnel diode comprising;

a PRJ (program junction) region formed within a semiconductor substrate;

a tunnel layer formed on said PRJ region;

a floating gate electrode formed over said tunnel layer;

a lightly doped region comprised of a first dopant of a first conductivity type formed within said PRJ region on a side of said floating gate electrode;

a highly doped region comprised of a second dopant of a second conductivity type formed within said PRJ region, wherein said highly doped region is formed to contact a side of said lightly doped region further away from said floating gate electrode;

and wherein said first conductivity type of said lightly doped region is opposite to said second conductivity type of said highly doped region;

and wherein said floating gate electrode of said tunnel diode is coupled to said floating gate node of said EEPROM memory cell, and wherein said highly doped region of said tunnel diode is coupled to a source of said write transistor of said EEPROM memory cell.

7. The EEPROM memory cell of claim 6, wherein said lightly doped region of said tunnel diode is formed when said first dopant is implanted into exposed regions of said PRJ region, with said gate electrode acting as a mask.

8. The EEPROM memory cell of claim 7, wherein said tunnel diode further comprises:

a sidewall spacer formed at said side of said gate electrode;

and wherein said highly doped region is formed when said second dopant is implanted into exposed regions of said PRJ region, with said gate electrode and said sidewall spacer acting as a mask.

9. The EEPROM memory cell of claim 6, wherein said first conductivity type of said first dopant for forming said lightly doped region is of P-type conductivity, and wherein said second conductivity type of said second dopant for forming said highly doped region is of N-type conductivity.

10. The EEPROM memory cell of claim 6, wherein said tunnel layer is comprised of oxide, and wherein said floating gate electrode is comprised of polysilicon.