Field-effect semiconductor devices

• US 6,600,194 B2
• Filed: 03/09/2001
• Issued: 07/29/2003
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Dalen, Rob, Hijzen, Erwin A., Hueting, Raymond J. E.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): VU, QUANG D
• Application Number:
  US09/803,325
• Publication Number:
  US 20010020720A1
• Time in Patent Office: 872 Days
• Field of Search: 257/302, 257/327-333, 257/341-344, 257/346, 438/259, 438/270, 438/271, 438/277, 438/588, 438/589
• US Class Current: 257/331
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722

Abstract

A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Claims

1. A field-effect semiconductor device comprising a semiconductor body having a plurality of side-by-side device cells at one major surface of the body, wherein each device cell has a source region that is separated by a channel-accommodating region of a first conductivity type from an underlying drain region of an opposite, second conductivity type, a gate electrode is capacitively coupled to the channel-accommodating region to control a conduction channel between the source and drain regions, and the device has at least one drain connection that extends in a drain trench from the one major surface to the underlying drain region, characterized in that the channel-accommodating region extends laterally to the drain trench, the drain trench extends through the thickness of the channel-accommodating region to the underlying drain region, the drain connection is separated from the channel-accommodating region by an intermediate insulating layer on side-walls of the drain trench, and wherein the drain region comprises a more highly doped electrode region underlying a less highly doped drift region, and the drain connection in the drain trench extends through the thickness of both the channel-accommodating region and the drain drift region to reach the more highly doped drain ode region.

2. A device as claimed in claim 1 further characterised in that the drain trench extends through a cell comprising a source region that is laterally separated from the drain trench by an intermediate part of the channel-accommodating region, which intermediate part of the channel-accommodating region is outside the control of the gate electrode.

3. A device as claimed in claim 1 further characterised in that the gate electrode extends in a gate trench through the thickness of the channel-accommodating region, and the source region of each cell is adjacent to the gate trench at the one major surface.

4. A device as claimed in claim 3, further characterised in that the gate trench is lined with a gate dielectric layer that is thinner than the intermediate insulating layer on the side walls of the_drain trench.

5. A device as claimed in claim 1, further characterized in that the drain drift region has a dopant concentration of the second conductivity type that is less than a conductivity-type-determining dopant concentration of the first conductivity type of the channel-accommodating region.

6. A device as claimed in claim 1 further characterised in that the drain region comprises a monocrystalline substrate of the second conductivity type, and the channel-accommodating region is present in an epitaxial layer on the monocrystalline substrate.

7. A field-effect semiconductor device comprising a semiconductor body having a plurality of side-by-side device cells at one major surface of the body, wherein each device cell has a source region that is separated by a channel-accommodating region of a first conductivity type from an underlying drain region of an opposite, second conductivity type, a gate electrode is capacitively coupled to the channel-accommodating region to control a conduction channel between the source and drain regions, and the device has at least one drain connection that extends in a drain trench from the one major surface to the underlying drain region, characterized in that the channel-accommodating region extends laterally to the drain trench, the drain trench extends through the thickness of the channel-accommodating region to the underlying drain region, the drain connection is separated from the channel-accommodating region by an intermediate insulating layer on side-walls of the drain trench, and the drain trench extends through a connection cell that is laterally surrounded by device cells without a drain trench.

8. The device as claimed in claim 7, further characterized in that, each device cell comprises a source region which is laterally separated from the drain trench by an intermediate part of the channel-accommodating region that is outside the control of the gate electrode.