Method and apparatus for probing an integrated circuit through capacitive coupling

• US 6,600,325 B2
• Filed: 02/06/2001
• Issued: 07/29/2003
• Est. Priority Date: 02/06/2001
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Sutherland, Ivan E., Coates, William S., Bosnyak, Robert J.
• Primary Examiner(s): Le, N.
• Assistant Examiner(s): Teresinski, John
• Application Number:
  US09/778,622
• Publication Number:
  US 20020105337A1
• Time in Patent Office: 903 Days
• Field of Search: 324/519, 324/513, 324/758, 324/555, 324/665, 324/686, 324/690
• US Class Current: 324/519
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/312 by capacitive methods

Abstract

One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

Claims

1. A method for capacitively probing electrical signals within an integrated circuit, comprising:

placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit, wherein a size of the probe conductor and the target conductor is commensurate with a smallest feature found on the integrated circuit;

wherein the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor;

detecting a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor;

determining a logic value for the target conductor from the change in the probe voltage; and

allowing testing circuitry coupled to the probe conductor to gather the logic value, wherein the testing circuitry is integrated into the probe conductor;

whereby the size of the probe conductor and the target conductor allows testing of the integrated circuit independent of a mounting substrate.

2. The method of claim 1, wherein determining the logic value for the target conductor involves:

determining that the logic value for the target conductor is a first value if the probe voltage decreases; and

determining that the logic value for the target conductor is a second value if the probe voltage increases.

3. The method of claim 1, wherein the target conductor is located in a highest metal layer of the integrated circuit.

4. The method of claim 1, wherein placing the probe conductor in close proximity to the target conductor involves aligning the probe conductor with the target conductor using at least one of:

an electrical alignment mechanism;

a mechanical alignment mechanism;

an optical alignment mechanism; and

a mechanism that includes micro-machined silicon structures that are located on-chip.

5. The method of claim 1,

wherein the probe conductor is located on a second integrated circuit;

and

wherein the target conductor is used to drive a value onto the second integrated circuit through the probe conductor.

6. The method of claim 1,

wherein the target conductor includes a plurality of target conductors disposed on a surface of the integrated circuit;

and

wherein the probe conductor includes a plurality of probe conductors disposed on a surface of a second integrated circuit, so that plurality of probe conductors can simultaneously monitor the plurality of target conductors when the plurality of probe conductors are aligned with the plurality of target conductors.

7. The method of claim 6, wherein the plurality of probe conductors are organized into a two-dimensional grid on the second integrated circuit.

8. The method of claim 6, wherein the method further comprises routing a plurality of target signals from within the integrated circuit to the plurality of target conductors during design of the integrated circuit, so that the plurality of target signals can be monitored by the plurality of probe conductors.

9. The method of claim 1, wherein the target conductor includes a bonding pad of the integrated circuit.

10. The method of claim 1, further comprising causing a liquid dielectric to be placed between the probe conductor and a target conductor.

11. An apparatus that capacitively probes electrical signals within an integrated circuit, comprising:

a probe conductor;

an alignment mechanism, coupled to the probe conductor, that is configured to place the probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit, so that the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor;

wherein a size of the probe conductor and the target conductor is commensurate with a smallest feature found on the integrated circuit;

a detection mechanism, coupled to the probe conductor, that is configured to detect a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor;

a logic value generation mechanism, coupled to the detection mechanism, that is configured to determine a logic value for the target conductor from the change in the probe voltage; and

testing circuitry coupled to the probe conductor that is configured to gather the logic value, wherein the testing circuitry is integrated into the probe conductor;

whereby the size of the probe conductor and the target conductor allows testing of the integrated circuit independent of a mounting substrate.

12. The apparatus of claim 11, wherein the logic value generation mechanism is configured to:

determine that the logic value for the target conductor is a first value if the probe voltage decreases; and

determine that the logic value for the target conductor is a second value if the probe voltage increases.

13. The apparatus of claim 11, wherein the target conductor is located in a highest metal layer of the integrated circuit.

14. The apparatus of claim 11, wherein the alignment mechanism includes at least one of:

an electrical alignment mechanism;

a mechanical alignment mechanism;

an optical alignment mechanism; and

a mechanism that includes micro-machined silicon structures that are located on-chip.

15. The apparatus of claim 11,

wherein the probe conductor is located on a second integrated circuit;

and

wherein the target conductor is configured to drive a value onto the second integrated circuit through the probe conductor.

16. The apparatus of claim 11,

wherein the target conductor includes a plurality of target conductors disposed on a surface of the integrated circuit;

and

wherein the probe conductor includes a plurality of probe conductors disposed on a surface of a second integrated circuit, so that plurality of probe conductors can simultaneously monitor the plurality of target conductors when the plurality of probe conductors are aligned with the plurality of target conductors.

17. The apparatus of claim 16, wherein the plurality of probe conductors are organized into a two-dimensional grid on the second integrated circuit.

18. The apparatus of claim 16, wherein the integrated circuit includes a plurality of routing lines for routing a plurality of target signals from within the integrated circuit to the plurality of target conductors disposed on the surface of the integrated circuit, so that the plurality of target signals can be monitored by the plurality of probe conductors.

19. The apparatus of claim 11, wherein the target conductor includes a bonding pad of the integrated circuit.

20. The apparatus of claim 11, further comprising a mechanism that is configured to cause a liquid dielectric to be placed between the probe conductor and a target conductor.

21. An apparatus that capacitively probes electrical signals within an integrated circuit, comprising:

a probe conductor;

an alignment mechanism, coupled to the probe conductor, that is configured to place the probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit, so that the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor;

wherein a size of the probe conductor and the target conductor is commensurate with a smallest feature found on the integrated circuit a detection mechanism, coupled to the probe conductor, that is configured to detect a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor;

a login value generation mechanism, coupled to the detection mechanism, that is configured to output a first value if the probe voltage decreases, and to output a second value if the probe voltage increases; and

a testing circuit coupled to the probe conductor that is configured to gather an output of the logic value generation mechanism, wherein the testing circuit is integrated into the probe conductor;

wherein the probe conductor includes a plurality of probe conductors disposed on a surface of a second integrated circuit, so that plurality of probe conductors can simultaneously monitor a plurality of target conductors disposed on a surface of the integrated circuit;

whereby the size of the probe conductor and the target conductor allows testing of the integrated circuit independent of a mounting substrate.