Loop filter architecture

• US 6,600,351 B2
• Filed: 02/08/2002
• Issued: 07/29/2003
• Est. Priority Date: 07/31/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cipriani, Stefano, Bisanti, Biagio, Coppola, Francesco
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/072,094
• Publication Number:
  US 20030025538A1
• Time in Patent Office: 536 Days
• Field of Search: 327/155, 327/156, 327/157, 327/147, 327/146, 327/148, 331/17, 331/DIG.2, 331/25, 375/294, 375/375, 375/376
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop

Abstract

A phase-lock loop (PLL) filter architecture includes a first charge pump (508) and a second change pump (510). The second charge pump (510) operates in opposite phase of the first charge pump (508) in order to take away excess charge from the loop filter capacitor(s). By using a second charge pump as described, the PLL filter does not require the use of a large capacitor and can therefore be integrated.

Claims

1. A phase-lock-loop (PLL) architecture comprising:

a loop filter having at least one capacitor;

a first charge pump coupled to the loop filter; and

a second charge pump coupled to the loop filter, said second charge pump operating in substantially opposite phase to said first charge pump in order to reduce the value of the capacitor.

2. A PLL architecture as defined in claim 1, wherein the loop filter comprises:

an input port;

a first capacitor coupled to said input port;

a first resistor coupled to said input port;

a second capacitor coupled to the first resistor, said first resistor and second capacitor coupled in parallel to said first capacitor.

3. A phase-lock-loop (PLL) architecture comprising:

a loop filter having at least one capacitor, the loop filter further including;

an input port;

a first capacitor coupled to said input port;

a first resistor coupled to said input port; and

a second capacitor coupled to the first resistor, said first resistor and second capacitor coupled in parallel to said first capacitor;

a first charge pump coupled to the loop filter; and

a second charge pump coupled to the loop filter, said second charge pump operating in substantially opposite phase to said first charge pump in order to reduce the value of the capacitor, and the first charge pump is coupled to the loop filter'"'"'s input port and the second charge pump is coupled between said first resistor and said second capacitor.

4. A PLL architecture as defined in claim 3, further comprising a voltage-controlled oscillator coupled to the loop filter.

5. A PLL architecture as defined in claim 3, wherein the loop filter comprises a type 2 PLL loop filter.

6. An integratable filter, comprising:

a first current source;

a filter section having an input and said first current source is coupled to the input,

said filter section including at least one capacitor; and

a second current source operating in opposite phase to the first current source and coupled to the at least one capacitor in order to reduce any excess charge applied to the at least one capacitor.

7. An integratable filter as defined in claim 6 wherein said first and second current sources comprise charge pumps.

8. An integratable filter as defined in claim 7, wherein said filter section comprises a loop filter.