Active interposer technology for high performance CMOS packaging application

• US 6,600,364 B1
• Filed: 01/05/1999
• Issued: 07/29/2003
• Est. Priority Date: 01/05/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mu, Xiao-Chun, Liang, Chunlin
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/225,418
• Time in Patent Office: 1,666 Days
• Field of Search: 327/564-566, 439/620, 361/767-771, 361/785, 361/807, 361/811
• US Class Current: 327/564
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

An integrated circuit assembly that includes an integrated circuit which is connected to an interposer. The integrated circuit may include a logic circuit which generates an output signal. The interposer may include a driver circuit that regenerates the output signal. The interposer may also contain a clock signal that is connected to the logic circuit. Separating the driver circuit from the integrated circuit may provide an assembly which reduces the amount of noise in the logic circuit created by the driver circuit switching states. Additionally, providing the clock circuit on the interposer allows the clock to be fabricated with a more robust process than the logic circuit of the integrated circuit.

Claims

1. An integrated circuit assembly, comprising:

an integrated circuit including a logic circuit and a memory circuit; and

,

an interposer that is connected to said integrated circuit mounted thereon, said interposer including (1) a power plane, a ground plane, and a dielectric material placed between said power plane and said ground plane to form a filtering capacitor, (2) a clock circuit to generate a clock signal that is transmitted to said memory circuit, and (3) a driver circuit to regenerate an output signal generated by the logic circuit.

2. The assembly of claim 1, wherein:

said internal ground plane being located between said internal power plane and said integrated circuit to shield said integrated circuit from noise generated within said internal power plane.

3. The assembly of claim 1, wherein said ground plane of the interposer is coupled between the power plane and the integrated circuit.

4. The assembly of claim 1, wherein said power plane of the interposer is coupled to the logic circuit and a power supply.

5. The assembly of claim 1, further comprising an underfill epoxy material dispensed between a bottom surface of said integrated circuit and a top surface of said interposer.

6. The assembly of claim 1, wherein said power bus on said external surface of said interposer including at least two interconnected power buses.

7. The assembly of claim 1, wherein said ground bus on said external surface of said interposer including at least two interconnected ground buses.

8. The assembly of claim 1, wherein said plurality of I/O contact pads being positioned between neighboring interconnected ground buses.

9. An electronic assembly comprising:

a circuit board;

an integrated circuit including a core logic and a memory circuit; and

,

an interposer coupled to both said circuit board and said integrated circuit mounted thereon, said interposer including (1) a power plane, a ground plane, and a dielectric material placed between said power plane and said ground plane to form at least one filtering capacitor, (2) a clock circuit to generate a clock signal that is transmitted to said memory circuit of said integrated circuit, and (3) a driver circuit to regenerate an output signal previously generated by said core logic of the integrated circuit.

10. The electronic assembly of claim 9, further comprising an underfill epoxy material dispensed between a bottom surface of said integrated circuit and a top surface of said interposer.

11. The electronic assembly of claim 9, wherein said integrated circuit is a microprocessor.

12. The electronic assembly of claim 11, wherein said microprocessor including output pads of which at least one output pad being coupled to the driver circuit.

13. The electronic assembly of claim 11 further comprising an encapsulant enclosing said integrated circuit.

14. The electronic assembly of claim 9, wherein an external surface of said interposer is adapted to include a power bus, a ground bus and a plurality of input/output (I/O) contact pads for coupling to I/O die pads of said integrated circuit.

15. The electronic assembly of claim 14, wherein said power bus on said external surface of said interposer including at least two interconnected power buses.

16. The electronic assembly of claim 14, wherein said ground bus on said external surface of said interposer including at least two interconnected ground buses.

17. The electronic assembly of claim 16, wherein said plurality of I/O contact pads being positioned between neighboring interconnected ground buses.