Active interposer technology for high performance CMOS packaging application
First Claim
1. An integrated circuit assembly, comprising:
- an integrated circuit including a logic circuit and a memory circuit; and
, an interposer that is connected to said integrated circuit mounted thereon, said interposer including (1) a power plane, a ground plane, and a dielectric material placed between said power plane and said ground plane to form a filtering capacitor, (2) a clock circuit to generate a clock signal that is transmitted to said memory circuit, and (3) a driver circuit to regenerate an output signal generated by the logic circuit.
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Accused Products
Abstract
An integrated circuit assembly that includes an integrated circuit which is connected to an interposer. The integrated circuit may include a logic circuit which generates an output signal. The interposer may include a driver circuit that regenerates the output signal. The interposer may also contain a clock signal that is connected to the logic circuit. Separating the driver circuit from the integrated circuit may provide an assembly which reduces the amount of noise in the logic circuit created by the driver circuit switching states. Additionally, providing the clock circuit on the interposer allows the clock to be fabricated with a more robust process than the logic circuit of the integrated circuit.
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Citations
17 Claims
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1. An integrated circuit assembly, comprising:
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an integrated circuit including a logic circuit and a memory circuit; and
,an interposer that is connected to said integrated circuit mounted thereon, said interposer including (1) a power plane, a ground plane, and a dielectric material placed between said power plane and said ground plane to form a filtering capacitor, (2) a clock circuit to generate a clock signal that is transmitted to said memory circuit, and (3) a driver circuit to regenerate an output signal generated by the logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
said internal ground plane being located between said internal power plane and said integrated circuit to shield said integrated circuit from noise generated within said internal power plane.
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3. The assembly of claim 1, wherein said ground plane of the interposer is coupled between the power plane and the integrated circuit.
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4. The assembly of claim 1, wherein said power plane of the interposer is coupled to the logic circuit and a power supply.
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5. The assembly of claim 1, further comprising an underfill epoxy material dispensed between a bottom surface of said integrated circuit and a top surface of said interposer.
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6. The assembly of claim 1, wherein said power bus on said external surface of said interposer including at least two interconnected power buses.
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7. The assembly of claim 1, wherein said ground bus on said external surface of said interposer including at least two interconnected ground buses.
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8. The assembly of claim 1, wherein said plurality of I/O contact pads being positioned between neighboring interconnected ground buses.
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9. An electronic assembly comprising:
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a circuit board;
an integrated circuit including a core logic and a memory circuit; and
,an interposer coupled to both said circuit board and said integrated circuit mounted thereon, said interposer including (1) a power plane, a ground plane, and a dielectric material placed between said power plane and said ground plane to form at least one filtering capacitor, (2) a clock circuit to generate a clock signal that is transmitted to said memory circuit of said integrated circuit, and (3) a driver circuit to regenerate an output signal previously generated by said core logic of the integrated circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification