High resolution, high speed, low power switched capacitor digital to analog converter

• US 6,600,437 B1
• Filed: 04/01/2002
• Issued: 07/29/2003
• Est. Priority Date: 04/01/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Confalonieri, Pierangelo, Zamprogno, Marco, Nagari, Angelo
• Primary Examiner(s): Wamsley, Patrick
• Application Number:
  US10/115,272
• Time in Patent Office: 484 Days
• Field of Search: 341/144, 341/145, 341/150, 341/172, 341/120, 341/143, 327/553, 327/93, 327/554, 331/111, 331/44
• US Class Current: 341/150
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy the relationship: (2^p−1)·C_s−C_ATT=2^p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

Claims

1. A switched capacitor digital to analog converter for providing an analog output signal corresponding to a digital input code, comprising:

a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode connected to a first common node and a second electrode connected through respective controllable switching means to either one of a first and second reference voltage terminals;

a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode connected to a second common node and a second electrode connected through respective controllable switching means to either one of said first and second reference voltage terminals;

a coupling capacitor with a first electrode connected to the first common node and a second electrode connected to the second common node;

control means coupled to the controllable switching means of the first and second converter segments to open or close selectively connections to the first and second reference voltage terminals depending on binary values of bits of the digital input code;

an output terminal connected to the second common node for providing the analog output signal as a function of the digital input code; and

capacitance means permanently connected between the first common node and a reference voltage terminal;

the coupling capacitor and the capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy a relationship;

(2^p−

1)·

C_s−

C_ATT=2^p·

C, where p is a number of bits coded in the first converter segment and C is the unit capacitance.

2. The converter of claim 1 wherein the reference voltage terminal to which the capacitance means are connected is a third reference voltage terminal, the capacitance means including first, second, and third capacitors coupled respectively between the first common node and the first, second, and third reference voltage terminals.

3. The converter of claim 2 wherein the capacitance means further includes a first switch coupled between the first capacitor and the first reference voltage terminal and a second switch coupled between the second capacitor and the second reference voltage terminal, the converter further comprising a bit register having first and second control outputs respectively coupled to respective control terminals of the first and second switches.

4. The converter of claim 1, wherein the capacitor with a smallest capacitance in the first converter segment has substantially a same capacitance as a capacitor with a smallest capacitance in the second converter segment.

5. The converter of claim 1, wherein the capacitance means comprises at least one capacitor having a first electrode connected to the first common node and a second electrode connected, through associated controllable switching means, to either one of said first and second reference voltage terminals, and the control means are coupled to the controllable switching means associated with said at least one capacitor to open or close the connection to the first and second reference voltage terminals depending on binary values of at least one bit of a correction digital code.

6. The converter of claim 1 wherein the first and second converter segments, coupling capacitor, control means, output terminal, and capacitance means are part of a first circuit arrangement, the converter further comprising:

a second circuit arrangement that includes first and second converter segments, a coupling capacitor, control means, an output terminal, and capacitance means; and

a differential signal detector having first and second inputs respectively coupled to outputs of the first and second circuit arrangements, and having an output at which a differential signal is produced based on signals received from the outputs of the first and second circuit.

7. A switched capacitor digital to analog converter for providing an analog output signal corresponding to a digital input code, comprising:

a first converter segment having a first array of switches and a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of the capacitors being connected in series with a corresponding one of the switches to a first common node and;

a second converter segment having a second array of switches and a second array of binary weighted capacitors with respective capacitances that are integer multiples of the unit capacitance, each of the capacitors of the second converter being connected in series with a corresponding one of the switches of the second converter to a second common node;

a coupling capacitor connected between the first and second common nodes;

control lines coupled to the switches of the first and second converter segments to open or close selectively the switches depending on binary values of bits of the digital input code; and

a capacitive element permanently connected between the first common node and a first reference voltage terminal, the coupling capacitor and the capacitive element having respective capacitances that are integer multiples of the unit capacitance.

8. The converter of claim 7 wherein the switches of the first array of switches are coupled respectively between a second reference voltage terminal and the corresponding capacitors of the first array of binary weighted capacitors and the switches of the second array of switches are coupled respectively between a third reference voltage terminal and the corresponding capacitors of the second array of binary weighted capacitors.

9. The converter of claim 8 wherein the capacitive element includes first, second, and third capacitors coupled respectively between the first common node and the first, second, and third reference voltage terminals.

10. The converter of claim 9 wherein the capacitive element further includes a first switch coupled between the second capacitor and the second reference voltage terminal and a second switch coupled between the third capacitor and the third reference voltage terminal, the converter further comprising a bit register having first and second control outputs respectively coupled to respective control terminals of the first and second switches.

11. The converter of claim 7 wherein the capacitor with a smallest capacitance in the first converter segment has substantially a same capacitance as a capacitor with a smallest capacitance in the second converter segment.

12. A switched capacitor digital to analog converter for providing an analog output signal corresponding to a digital input code, comprising:

a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode connected to a first common node and a second electrode connected through respective controllable switching means to either one of a first and second reference voltage terminals;

a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode connected to a second common node and a second electrode connected through respective controllable switching means to either one of said first and second reference voltage terminals;

a coupling capacitor with a first electrode connected to the first common node and a second electrode connected to the second common node;

control means coupled to the controllable switching means of the first and second converter segments to open or close selectively connections to the first and second reference voltage terminals depending on binary values of bits of the digital input code;

an output terminal connected to the second common node for providing the analog output signal as a function of the digital input code; and

capacitance means connected between the first common node and a reference voltage terminal;

the coupling capacitor and the capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy a relationship;

(2^p−

1)·

C_s−

C_ATT=2^p·

C, where p is a number of bits coded in the first converter segment and C is the unit capacitance, wherein the reference voltage terminal to which the capacitance means are connected is a third reference voltage terminal, the capacitance means including first, second, and third capacitors coupled respectively between the first common node and the first, second, and third reference voltage terminals.

13. The converter of claim 12 wherein the capacitance means further includes a first switch coupled between the first capacitor and the first reference voltage terminal and a second switch coupled between the second capacitor and the second reference voltage terminal, the converter further comprising a bit register having first and second control outputs respectively coupled to respective control terminals of the first and second switches.

14. A switched capacitor digital to analog converter for providing an analog output signal corresponding to a digital input code, comprising:

a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode connected to a first common node and a second electrode connected through respective controllable switching means to either one of a first and second reference voltage terminals;

a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode connected to a second common node and a second electrode connected through respective controllable switching means to either one of said first and second reference voltage terminals;

a coupling capacitor with a first electrode connected to the first common node and a second electrode connected to the second common node;

control means coupled to the controllable switching means of the first and second converter segments to open or close selectively connections to the first and second reference voltage terminals depending on binary values of bits of the digital input code;

an output terminal connected to the second common node for providing the analog output signal as a function of the digital input code; and

capacitance means connected between the first common node and a reference voltage terminal;

the coupling capacitor and the capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy a relationship;

(2^p−

1)·

C_s−

C_ATT=2^p·

C, where p is a number of bits coded in the first converter segment and C is the unit capacitance, wherein the first and second converter segments, coupling capacitor, control means, output terminal, and capacitance means are part of a first circuit arrangement, the converter further comprising;

a second circuit arrangement that includes first and second converter segments, a coupling capacitor, control means, an output terminal, and capacitance means; and

a differential signal detector having first and second inputs respectively coupled to outputs of the first and second circuit arrangements, and having an output at which a differential signal is produced based on signals received from the outputs of the first and second circuit.

15. A switched capacitor digital to analog converter for providing an analog output signal corresponding to a digital input code, comprising:

a first converter segment having a first array of switches and a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of the capacitors being connected in series with a corresponding one of the switches to a first common node and;

a second converter segment having a second array of switches and a second array of binary weighted capacitors with respective capacitances that are integer multiples of the unit capacitance, each of the capacitors of the second converter being connected in series with a corresponding one of the switches of the second converter to a second common node;

a coupling capacitor connected between the first and second common nodes;

control lines coupled to the switches of the first and second converter segments to open or close selectively the switches depending on binary values of bits of the digital input code; and

a capacitive element connected between the first common node and a first reference voltage terminal, the coupling capacitor and the capacitive element having respective capacitances that are integer multiples of the unit capacitance, wherein the switches of the first array of switches are coupled respectively between a second reference voltage terminal and the corresponding capacitors of the first array of binary weighted capacitors and the switches of the second array of switches are coupled respectively between a third reference voltage terminal and the corresponding capacitors of the second array of binary weighted capacitors.

16. The converter of claim 15 wherein the capacitive element includes first, second, and third capacitors coupled respectively between the first common node and the first, second, and third reference voltage terminals.

17. The converter of claim 16 wherein the capacitive element further includes a first switch coupled between the second capacitor and the second reference voltage terminal and a second switch coupled between the third capacitor and the third reference voltage terminal, the converter further comprising a bit register having first and second control outputs respectively coupled to respective control terminals of the first and second switches.