Capacitor mismatch independent gain stage for pipeline analog to digital converters

• US 6,600,440 B1
• Filed: 08/15/2001
• Issued: 07/29/2003
• Est. Priority Date: 08/15/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Sakurai, Satoshi
• Primary Examiner(s): JeanGlaude, Jean Bruner
• Application Number:
  US09/930,810
• Time in Patent Office: 713 Days
• Field of Search: 341/161, 341/155, 341/172, 341/120, 341/118
• US Class Current: 341/172
• CPC Class Codes: H03M 1/0619 by dividing out the errors, i.e. using a ratiometric arrangement
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/442 using switched capacitors
• CPC Class Codes: H03M 1/70 Automatic control for modifying converter range

Abstract

A method and apparatus are arranged for minimizing the effects of capacitor mismatch errors in pipelined analog-to-digital converters (ADC). The virtual elimination of capacitor mismatch effects is achieved without trading comparator offset margin by an appropriate selection of comparator circuits'"'"' reference signals and the inclusion of a plurality of capacitors that are switched into an appropriate feedback position. The appropriate feedback position in the switched capacitor amplifier circuit is determined based on the operating region. For each of k pipeline stage, a method includes: determining an operating region of a sampled analog input signal for a predetermined transfer curve, and computing digital code bits and an improved residue signal for this stage based on the determined operating region, and then computing a final conversion code from the digital code bits of the k pipeline stages.

Claims

1. An apparatus for producing digital output signals from an analog input signal in a pipelined stage that includes a sample mode and a hold mode, the apparatus comprising:

a first capacitor circuit that is coupled to the analog input signal during the sample mode such that the first capacitor circuit is charged by the analog input signal;

a second capacitor circuit that is coupled to the analog input signal during the sample mode such that the second capacitor circuit is charged by the analog input signal;

a third capacitor circuit that is coupled to a circuit ground potential during the sample mode such that the third capacitor is discharged;

a comparator circuit that is coupled to the analog input signal, and first and second sampling reference signals that are pre-selected to minimize transition height errors, the comparator circuit providing an output code in response to the analog input signal and the first and second sampling reference signals, wherein the output code correspond to one of at least three operating regions for the analog input signal during the sample mode;

an amplifier circuit that is coupled to the first, second, and third capacitance circuits during the hold mode;

a first selection circuit that is arranged to couple a selected one of the first, second, and third capacitance circuits between an input and an output of the amplifier circuit in response to the output code during the hold mode; and

a second selection circuit that is arranged to couple the other of the capacitor circuits between a respective hold reference signal and the input of the amplifier circuit, wherein the hold reference signals and the selected capacitor are determined by the output code, and the output of the amplifier circuit during the hold mode corresponds to a residue signal in a pipelined converter.

2. The apparatus of claim 1, wherein the capacitor circuits each have capacitance values that are substantially the same.

3. The apparatus of claim 1, wherein each of the hold reference signals correspond to one of the values of +V_ref/2 and −

V_ref/2, wherein V_ref corresponds to the absolute value of the maximum conversion range of the analog input signal.

4. The apparatus of claim 1, wherein the first and second sampling reference signals correspond to +V_ref/4 and −

V_ref/4.

5. The apparatus as in claim 1, further comprising a fourth capacitor circuit that is coupled to the circuit ground potential during the sample mode such that the fourth capacitor is discharged, a third sampling reference signal that is coupled to the comparator circuit, wherein the comparator circuit is arranged to provide an output code in response to the analog input signal, and the first, second and third sampling reference signals such that the output code corresponds to one of at least four operating regions for the analog input signal during the sample mode, the first selection circuit is arranged to couple a selected one of the first, second, third and fourth capacitance circuits between an input and an output of the amplifier circuit in response to the output code, and the second selection circuit is arranged to couple the other of the capacitor circuits between a respective hold reference signal and the input of the amplifier circuit, wherein the hold reference signals and the selected capacitor are determined by the output code, and the output of the amplifier circuit during the hold mode corresponds to a residue signal in a pipelined converter.

6. The apparatus of claim 5, wherein the third sampling reference signal corresponds to the circuit ground potential.

7. The apparatus as in claim 1, wherein the output code includes a number of effective bits and each of the effective bits is associated with a corresponding operating region for the analog input signal during the sample mode.

8. An apparatus in claim 1, wherein the analog input signal is a differential signal and the residue signal is another differential signal.

9. A circuit for minimizing the effects of capacitor mismatch errors in a conversion code generated by a k-pipelined analog to digital converter in response to an analog input signal, the circuit comprising:

k pipeline stages that are arranged in sequence such that an input signal to each subsequent pipeline stage is provided by a residue signal from a preceding pipeline stage, each pipeline stage including a plurality of capacitors, a comparison circuit, an amplifier circuit, wherein one of the plurality of capacitors is coupled to a ground potential during a sampling mode, and one of the plurality of capacitors is selectively switched into a feedback position of the amplifier circuit during a hold mode, the comparison circuit is arranged to produce a plurality of digital code bits, and the amplifier provides the residue signal in response to the input signal such that the plurality of digital code bits correspond to an operating region of the input signal, and a plurality of transition points define the operating regions such that transition height errors that occur from capacitor mismatches are minimized; and

a decoder logic circuit that is arranged to produce a conversion code in response to the plurality of digital code bits from each of the k pipeline stages.

10. A method for converting an analog input signal to a conversion code, in a converter with multiple pipelined stages, each pipelined stage including a plurality of capacitor circuits, comprising:

sampling the analog input signal from one of the analog input signal and an improved residue signal from a preceding one of the pipelined stages to produce a sampled analog signal, wherein at least one capacitor circuit of the plurality of capacitor circuits is coupled to a ground potential during sampling of the analog input signal;

comparing the sampled analog signal to transition points on a transfer curve, wherein the transition points are arranged to partition an analog input range into multiple operating regions;

providing a digital code in response to the comparison between the sampled analog signal and the transition points such that the digital code corresponds to a selected one of the multiple operating regions;

producing an improved residue signal in response to the digital code and the sampled analog input signal such that the improved residue signal corresponds to a point along the transfer curve in the selected one of the multiple operating regions; and

computing the conversion code from the digital codes from each stage in the pipelined converter, such that offset margins in the transfer curve that occur at the transition points are retained, and transition height errors that occur at the transition points are eliminated.

11. A method as in claim 10, wherein the step of comparing the sampled analog signal to transition points includes comparing the sampled analog signal to a first transition point that corresponds to V_ref/4 and comparing the sampled analog signal to a second transition point that corresponds to −

V_ref/4, and the transition points define three operating regions.

12. A method as in claim 10, wherein the step of comparing the sampled analog signal to transition points includes comparing the sampled analog signal to a first transition point that corresponds to V_ref/2, comparing the sampled analog signal to a second transition point that corresponds to zero, and comparing the sampled analog signal to a third transition point that corresponds to −

V_ref/2 such that the transition points define four operating regions.

13. An apparatus for converting an analog input signal to a conversion code, in a converter with multiple pipelined stages, each pipelined stage including a plurality of capacitors means, the apparatus comprising:

a means for sampling that is arranged to sample the analog input signal from one of the analog input signal and an improved residue signal from a preceding one of the pipelined stages to produce a sampled analog signal, wherein one capacitor means of the plurality of capacitor means in the sampling pipelined stage is coupled to a ground potential during sampling of the analog input signal;

a means for comparing that is arranged to compare the sampled analog signal to transition points on a transfer curve, wherein the transition points are arranged to partition an analog input range into multiple operating regions;

a means for providing that is arranged to provide a digital code in response to the comparison between the sampled analog signal and the transition points such that the digital code corresponds to a selected one of the multiple operating regions;

a means for producing that is arranged to produce an improved residue signal in response to the digital code and the sampled analog input signal such that the improved residue signal corresponds to a point along the transfer curve in the selected one of the multiple operating regions; and

a means for computing that is arranged to compute the conversion code from the digital codes from each stage in the pipelined converter, such that offset margins in the transfer curve that occur at the transition points are retained, and errors that occur at the transition points are minimized.

14. An apparatus as in claim 13, wherein the means for comparing includes a means for comparing that is arranged to compare the sampled analog signal to a first transition point that corresponds to V_ref/4 and a second means for comparing that is arranged to compare the sampled analog signal to a second transition point that corresponds to −

V_ref/4, such that the first and second the transition points define three operating regions.

15. An apparatus as in claim 13, wherein the means for comparing includes a means for comparing that is arranged to compare the sampled analog signal to a first transition point that corresponds to V_ref/2, a second means for comparing that is arranged to compare the sampled analog signal to a second transition point that corresponds to zero, and a means for comparing that is arranged to compare the sampled analog signal to a third transition point that corresponds to −

V_ref/2 such that the first, second, and third transition points define four operating regions.

16. An apparatus in claim 13, wherein the errors that are minimized include at least one of a transition height error, a gain error, and a pipeline stage saturation error that occur as a result of capacitor mismatches.