Driving circuit

• US 6,600,483 B1
• Filed: 08/30/2000
• Issued: 07/29/2003
• Est. Priority Date: 02/25/2000
• Status: Expired due to Fees

• Current Assignee: New Japan Radio Company Limited (Nisshinbo Holdings Incorporated)
• Original Assignee: New Japan Radio Company Limited (Nisshinbo Holdings Incorporated)
• Inventors: Kawano, Tomoyuki, Akita, Shinichi
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Shapiro, Leonid
• Application Number:
  US09/651,371
• Time in Patent Office: 1,063 Days
• Field of Search: 345/204-206, 345/242, 345/50, 345/55, 345/87, 345/92, 345/20, 345/89, 345/77, 345/94, 327/53, 327/54, 327/66, 330/253, 330/261, 326/68, 326/80, 326/81, 323/315, 323/312, 323/313
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: H03F 2203/30018 A series coupled active resistor and capacitor are coupled in a feedback circuit of a SEPP amplifier
• CPC Class Codes: H03F 2203/30036 A feedback circuit to stabilise the SEPP being used
• CPC Class Codes: H03F 2203/30057 the SEPP power transistors are realised as paralleled FETs, i.e. the push or the pull transistor
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45486 the CSC comprising two or more paralleled transistors as current source
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 2203/45658 the LC comprising two diodes of current mirrors
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45192 Folded cascode stages

Abstract

The present invention relates to a driving circuit used suitably for driving a capacitive load such as liquid crystal panel. The driving circuit of the present invention comprises a differential amplifying circuit, an output circuit and current control circuit. The output circuit is driven by an output signal of the differential amplifying circuit. A increased current signal is injected to the current control circuit for applying a positive feedback to increase an operating current of the differential amplifying circuit. A negative feedback for decreasing the increased current signal thus injected is also applied to the aforesaid current control circuit.

Claims

1. A driving circuit comprising,

a differential amplifying circuit,

an output circuit driven by an output signal of the differential amplifying circuit;

and

a current control circuit for applying a positive feedback in such that an increased current signal of an operating current on a noninverting side or an operating current on an inverting side of the differential amplifying circuit is injected to increase an operating current of the differential amplifying circuit;

wherein a negative feedback implemented by a recirculating transistor chain having a recirculating gain of less-than 1 for decreasing the increased current signal thus injected is applied to the aforesaid current control circuit,

wherein the aforesaid differential amplifying circuit is provided with a first current mirror circuit for supplying an electric current corresponding to an operating current on the noninverting side to an output section on the inverting side,

and a second current mirror circuit for supplying an electric current corresponding to an operating current on the inverting side to an output section on the noninverting side;

wherein an increased variation signal of either of the electric current supplied by the first current mirror circuit or the electric current supplied by the second current mirror circuit is injected to the aforesaid current control circuit as the aforesaid increased current signal.

2. The driving circuit of claim 1,

wherein a biasing current mirror circuit to add a current being proportional to the aforesaid increased current signal to the operating current of the aforesaid differential amplifying circuit, and a group of negative feedback current mirror circuits which is allowed to decrease the aforesaid increased current signal injected to the current control circuit are provided.

3. The driving circuit of claim 1, wherein the aforesaid current control circuit is provided with a delay capacitor charged by the aforesaid increased current signal thus injected.

4. The driving circuit of claim 2, wherein the aforesaid biasing current mirror circuit is provided with a delay capacitor charged by the aforesaid increased current signal thus injected.

5. A driving circuit comprising,

a differential amplifying circuit,

an output circuit driven by an output signal of the differential amplifying circuit;

and

a current control circuit for applying a positive feedback in such that an increased current signal of an operating current on a noninverting side or an operating current on an inverting side of the differential amplifying circuit is injected to increase an operating current of the differential amplifying circuit;

wherein a negative feedback implemented by a recirculating transistor chain having a recirculating gain of less than 1 for decreasing the increased current signal thus injected is applied to the aforesaid current control circuit,

wherein a biasing current mirror circuit to add a current being proportional to the aforesaid increased current signal to the operating current of the aforesaid differential amplifying circuit, and a group of negative feedback current mirror circuits which is allowed to decrease the aforesaid increased current signal injected to the current control circuit are provided,

wherein the aforesaid group of the negative feedback current mirror circuits is provided with a first current mirror circuit wherein the aforesaid increased current signal is injected to an output side thereof,

a second current mirror circuit wherein an electric current on the output side of the first current mirror circuit flows in a reference side thereof, while an electric current on its output side flows in the reference side of the aforesaid first current mirror circuit,

and a third current mirror circuit wherein an electric current on the reference side of the aforesaid first current mirror circuit flows in its reference side, while an electric current on its output side flows in the output side of the aforesaid first current mirror circuit;

and each magnification of the aforesaid first, second, and third current mirror circuits is set to a predetermined value, whereby the aforesaid increased current signal thus injected is allowed to decrease.

6. A driving circuit comprising,

a differential amplifying circuit

an output circuit driven by an output signal of the differential amplifying circuit;

and

a current control circuit for applying a positive feedback in such that an increased current signal of an operating current on a noninverting side or an operating current on an inverting side of the differential amplifying circuit is injected to increase an operating current of the differential amplifying circuit,

wherein a negative feedback for decreasing the increased current signal thus injected is applied to aforesaid current control circuit,

wherein a biasing current mirror circuit to add a current being proportional to the aforesaid increased current signal to the operating current of the aforesaid differential amplifying circuit, and a group of negative feedback current mirror circuits which is allowed to decrease the aforesaid increased current signal injected to the current control circuit arc provided,

wherein the aforesaid output circuit is constituted in such that a first transistor driven in response to an increased current signal of either of the operating current on the noninverting side or the operating current on the inverting side of the aforesaid differential amplifying circuit and a second transistor driven by a fixed bias voltage are connected serially between a high potential power source and a low potential power source, common connecting points of both the transistors are served for an output terminal, and a third transistor is connected in parallel to the aforesaid second transistor; and

the current control circuit to which is injected the other increased current signal of the operating current on the noninverting side or the operating current on the inverting side of the aforesaid differential amplifying circuit is provided with a load resistance for converting the aforesaid increased current signal thus injected into a voltage;

whereby the aforesaid third transistor is driven by the voltage produced in the load resistance.