Clock supply circuit

• US 6,600,575 B1
• Filed: 06/28/1999
• Issued: 07/29/2003
• Est. Priority Date: 07/22/1998
• Status: Expired due to Term

• Current Assignee: Oki Data Corporation (OKI Electric Industry Company Limited)
• Original Assignee: Oki Data Corporation (OKI Electric Industry Company Limited)
• Inventors: Kohara, Ryuichi
• Primary Examiner(s): Coles, Edward
• Assistant Examiner(s): CARTER, TIA A
• Application Number:
  US09/340,814
• Time in Patent Office: 1,492 Days
• Field of Search: 358/406, 358/409, 358/410, 358/411, 358/412, 347/11, 347/57, 347/249, 347/247, 347/250, 347/237, 327/295, 327/115, 327/117, 327/293, 327/296, 327/144, 327/145
• US Class Current: 358/406
• CPC Class Codes: H04N 1/00 Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
• CPC Class Codes: H04N 1/00933 Timing control or synchronising H04N1/00928, H04N1/00931, H04N1/00954 and H04N1/0096 take precedence

Abstract

A clock dividing section receives a system clock and generates and outputs clock signals of two or more types. Selectors select any of the clock signals of two or more types outputted by the clock dividing section and feed it to a printing control block or reading control block. A decision divider monitors operational states of each block and gives control so that a frequency to be supplied to a functional block in an idle state where any operation is not required is lower than that to be supplied to a functional block being in an active state. Power consumption of the whole custom IC can be more reduced compared with a configuration wherein a clock of fixed frequency is constantly supplied to each functional block and a noise can be controlled.

Claims

1. A clock supply circuit for feeding a clock signal to a functional block of an electronic apparatus having a functional block being operating based on a clock signal produced by dividing a system clock comprising:

a clock dividing section for generating said clock signal to be fed to said functional block by dividing said system clock; and

a control section for controlling a supply of said clock signal from said clock dividing section to said functional block depending on an active state of said functional block where a desired operation is required or on an idle state where no operation is required wherein said clock dividing section is adapted to generate a plurality of clock signals each having a different frequency and wherein said control section comprises selectors adapted to selectively output said plural clock signals fed by said clock dividing section, and a decision section adapted to control a selection operation of said selectors so that, in an active state of said functional block where said desired operation is required, a clock signal selected out of said plural clock signals having proper frequency is supplied to ensure adequate operations of said functional block and so that, in an idle state, a clock signal having a frequency being lower than that of said clock supplied in said state where said desired operation is required is fed to said functional block and wherein said electronic apparatus is equipped with a plurality of functional blocks and wherein said clock dividing section is adapted to generate a plurality of clock signals each having a different frequency and wherein each functional block is provided with one of the selectors for providing the selected frequency to the functional block.

2. The clock supply circuit according to claim 1, wherein said control section is provided with a counter used for detecting the termination of said desired operation of said each functional block and the frequency of a clock signal to be fed to said each functional block the termination of said desired operation of which is detected by said counter is made lower by said decision section.

3. The clock supply circuit according to claim 1, wherein said control section is further provided with a gate circuit adapted to allow or not to allow a supply of said clock signal to said functional block and the operation of said gate circuit is so controlled by said decision section that, in an active state of said functional block where said desired operation is required, said clock signal is supplied to said functional block to ensure proper operations of said functional block and that, in an idle state, the supply of said clock signal to said functional block is stopped.

10. The clock supply circuit according to claim 1, wherein said electronic apparatus, in the copying operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said highest frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a dock signal having said highest frequency to said functional block while it is in an active state.

11. The clock supply circuit according to claim 1, wherein said electronic apparatus, in the sending operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block regardless of whether said block is in an active or idle state.

12. The clock supply circuit according to claim 1, wherein said electronic apparatus, in the receiving operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block regardless of whether said block is in an active or idle state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said second functional block while it is in an active state.

4. A clock supply circuit for feeding a clock signal to a functional block of an electronic apparatus having a functional block being operating based on a clock signal produced by dividing a system clock comprising:

a clock dividing section for generating said clock signal to be fed to said functional block by dividing said system clock; and

a control section for controlling a supply of said clock signal from said clock dividing section to said functional block depending on an active state of said functional block where a desired operation is required or on an idle state where no operation is required wherein said electronic apparatus is provided with a first functional block to control reading of data and a second functional block to control printing operations, having a facsimile function and copying function and wherein said dividing section is adapted to generate a clock signal having three kinds of frequencies, i.e., lowest frequency, highest frequency and intermediate frequency to be fed to said first and second functional blocks and said clock signal to be fed to said functional block according to the active state and idle state of said each functional block is selected out of said clock signal having said lowest, highest and intermediate frequencies with reference to each of operational modes including copying, sending and receiving operation modes of said electronic apparatus.

5. The clock supply circuit according to claim 4, wherein said electronic apparatus, in the copying operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said highest frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a clock signal having said highest frequency to said functional block while it is in an active state.

6. The clock supply circuit according to claim 4, wherein said electronic apparatus, in the sending operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block regardless of whether said block is in an active or idle state.

7. The clock supply circuit according to claim 4, wherein said electronic apparatus, in the receiving operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block regardless of whether said block is in an active or idle state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said second functional block while it is in an active state.

8. The clock supply circuit according to claim 4, wherein said control section is provided with a counter used for detecting the termination of said desired operation of said each functional block and the frequency of a clock signal to be fed to said each functional block the termination of said desired operation of which is detected by said counter is made lower by said decision section.

9. The clock supply circuit according to claim 4, wherein said control section is further provided with a gate circuit adapted to allow or not to allow a supply of said clock signal to said functional block and the operation of said gate circuit is so controlled by said decision section that, in an active state of said functional block where said desired operation is required, said clock signal is supplied to said functional block to ensure proper operations of said functional block and that, in an idle state, the supply of said clock signal to said functional block is stopped.

13. A clock supply circuit for supplying clock signals to an electronic apparatus having a plurality of functional blocks, each functional block operating based on said clock signal, comprising:

a clock dividing section to receive and divide a system clock, and to output a plurality of clock signals with different frequencies;

a decision section for selecting one appropriate frequency from the plurality of clock signals to be supplied to one of the plurality of functional blocks based on an operating state signal of the one of said plurality of functional blocks and for outputting a decision signal as a frequency selection signal; and

at least one selector receiving at least two clock signals outputted from said dividing section and receiving said decision signal outputted from said decision section, selecting one of the received clock signals based on the received decision signal, and outputting said selected clock signal to said electronic apparatus for supplying said selected clock signal to said one of said functional blocks.

14. The clock supply circuit according to claim 13, wherein said clock dividing section is adapted to generate a plurality of clock signals each having a different frequency and wherein said control section comprises selectors adapted to selectively output said plural clock signals fed by said clock dividing section, and a decision section adapted to control a selection operation of said selectors so that, in an active state of said functional block where said desired operation is required, a clock signal selected out of said plural clock signals having proper frequency is supplied to ensure adequate operations of said functional block and so that, in an idle state, a clock signal having a frequency being lower than that of said clock supplied in said state where said desired operation is required is fed to said functional block.

15. The clock supply circuit according to claim 14, wherein said electronic apparatus is equipped with a plurality of functional blocks and wherein said clock dividing section is adapted to generate a plurality of clock signals each having a different frequency depending on each functional block and wherein each block is provided with each selector.

16. The clock supply circuit according to claim 15, wherein said control section is provided with a counter used for detecting the termination of said desired operation of said each functional block and the frequency of a clock signal to be fed to said each functional block the termination of said desired operation of which is detected by said counter is made lower by said decision section.

17. The clock supply circuit according to claim 15, wherein said control section is further provided with a gate circuit adapted to allow or not to allow a supply of said clock signal to said functional block and the operation of said gate circuit is so controlled by said decision section that, in an active state of said functional block where said desired operation is required, said clock signal is supplied to said functional block to ensure proper operations of said functional block and that, in an idle state, the supply of said clock signal to said functional block is stopped.

18. The clock supply circuit according to claim 13, wherein said control section comprises a gate circuit adapted to allow or not to allow the supply of said clock signal outputted from said clock dividing section to said functional block and a decision circuit adapted to give control to operations of said gate circuit so that, in an active state of said functional block where said desired operation is required, said clock signal is supplied to said functional block to ensure proper operations of said functional block and that, in an idle state, the supply of said clock signal to said functional block is stopped.

19. The clock supply circuit according to claim 13, wherein said electronic apparatus is provided with a first functional block to control reading of data and a second functional block to control printing operations, having a facsimile function and copying function and wherein said dividing section is adapted to generate a clock signal having three kinds of frequencies, i.e., lowest frequency, highest frequency and intermediate frequency to be fed to said first and second functional blocks and said clock signal to be fed to said functional block according to the active state and idle state of said each functional block is selected out of said clock signal having said lowest, highest and intermediate frequencies with reference to each of operational modes including copying, sending and receiving operation modes of said electronic apparatus.

20. The clock supply circuit according to claim 19, wherein said electronic apparatus, in the copying operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said highest frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a dock signal having said highest frequency to said functional block while it is in an active state.

21. The clock supply circuit according to claim 19, wherein said electronic apparatus, in the sending operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said first functional block while it is in an active state, or to supply a clock signal having said lowest frequency to said second functional block regardless of whether said block is in an active or idle state.

22. The clock supply circuit according to claim 19, wherein said electronic apparatus, in the receiving operation mode, is adapted to supply a clock signal having said lowest frequency to said first functional block regardless of whether said block is in an active or idle state, or to supply a clock signal having said lowest frequency to said second functional block while it is in an idle state and to supply a clock signal having said intermediate frequency to said second functional block while it is in an active state.

23. The clock supply circuit according to claim 13, wherein said operating state signal is output signal from said functional block.

24. The clock supply circuit according to claim 13, wherein when a plural number of said functional blocks are operating, said decision section decides a higher said frequency with respect to each operating functional block and when only one said functional block is operating, said decision section decides a lower said frequency with respect to the operating functional block.