Level shifter for converting a voltage level and a semiconductor memory device having the level shifter

• US 6,600,679 B2
• Filed: 12/27/2001
• Issued: 07/29/2003
• Est. Priority Date: 12/27/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanzawa, Toru, Watanabe, Kentaro
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/033,442
• Publication Number:
  US 20020080651A1
• Time in Patent Office: 579 Days
• Field of Search: 365/189.11, 365/154, 365/149, 365/226, 365/185.01, 365/230.06
• US Class Current: 365/189.11
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A level shifter comprises a latch circuit, a first capacitor and a second capacitor. The latch circuit has a first node and a second node set to a first voltage or a second voltage. The second node is set to the second voltage when the first node is set to the first voltage and the second node is set to the first voltage when the first node is set to the second voltage. A first terminal side of the first capacitor is connected to the first node. A first signal is supplied to a second terminal side of the first capacitor. A third terminal side of the second capacitor is connected to the second node. When the first signal is supplied to the second terminal side of the first capacitor, an inverted replica of the first signal is supplied to a fourth terminal side of the second capacitor.

Claims

1. A level shifter comprising:

a latch circuit having a first node and a second node set to a first voltage or a second voltage, said second node being set to said second voltage when said first node is set to said first voltage and said second node being set to said first voltage when said first node is set to said second voltage;

a first capacitor having a first terminal and a second terminal, said first terminal of said first capacitor being connected to said first node, a first signal being supplied to said second terminal of said first capacitor; and

a second capacitor having a third terminal and a fourth terminal, said third terminal of said second capacitor being connected to said second node, when said first signal is supplied to said second terminal of said first capacitor, an inverted replica of said first signal being supplied to said fourth terminal of said second capacitor.

2. The level shifter according to claim 1, wherein said latch circuit has a plurality of inverting elements including first and second inverting elements and, of said plurality of inverting elements, an output terminal of said first inverting element is connected to an input terminal of said second inverting element.

3. The level shifter according to claim 1, wherein, with VH and VL representing said first voltage and said second voltage, respectively, and Vh and Vl representing a first logical voltage of said first signal and second logical voltage of an inverted replica of said first signal, respectively, a value of VH−

Vh+Vl is smaller than a value of VL+Vh−

Vl.

4. The level shifter according to claim 3, wherein the value of VH−

Vh+Vl is larger than VL and the value of VL+Vh−

Vl is smaller than VH.

5. The level shifter according to claim 3, wherein a value of Vh−

VH is equal to or smaller than a value of VH−

VL and a value of Vl−

VL is equal to or smaller than the value of VH−

VL.

6. The level shifter according to claim 3, wherein a value of VH−

VL is smaller than a withstand voltage of the latch circuit.

7. The level shifter according to claim 3, further comprising a plurality of third inverting elements generating Vh and Vl.

8. The level shifter according to claim 7, wherein a value of Vh−

Vl is smaller than a withstand voltage of said third inverting element.

9. The level shifter according to claim 1, further comprising a resetting transistor initializing a potential on said first node and a potential on said second node.

10. A semiconductor memory device comprising:

a nonvolatile memory cell formed of a semiconductor substrate and having a floating gate and a control gate, said nonvolatile memory cell storing data by accumulating a charge amount in the floating gate;

a row decoder selecting and driving a word line connected to said control gate;

a driver controlling a potential of said semiconductor substrate;

a short circuit shorting said semiconductor substrate and said word line; and

a first level shifter having a first latch circuit, a first capacitor and a second capacitor,

said first latch circuit having a first node and a second node set to a first voltage or a second voltage, said second node being set to said second voltage when said first node is set to said first voltage and said second node being set to said first voltage when said first node is set to said second voltage

said first capacitor having a first terminal and a second terminal and said first terminal of said first capacitor being connected to said first node,

said second capacitor having a third terminal and a fourth terminal and said third terminal of said capacitor being connected to said second node,

wherein data erase operation of said nonvolatile memory cell is performed by applying a negative voltage to said word line and a positive voltage to said semiconductor substrate, said first level shifter allows a first signal to be supplied to said second terminal of said first capacitor and an inverted replica of said first signal to be supplied to said fourth terminal of said second capacitor to output a voltage different from the voltage of said first signal, and said short circuit shorts said semiconductor substrate and said word line in accordance with an output of said first level shifter after the data erase operation has been completed.

11. The semiconductor memory device according to claim 10, wherein said latch circuit has a plurality of inverting elements including a first inverting element and a second inverting element and, of said plurality of inverting elements, an output terminal of said first inverting element is connected to an input terminal of said second inverting element.

12. The semiconductor memory device according to claim 10, wherein, with VH and VL representing said first voltage and said second voltage, respectively, and Vh and Vl representing a first logical voltage of said first signal and a second logical voltage of an inverted replica of said first signal, a value of VH−

Vh+Vl is smaller than a value of VL+Vh−

Vl.

13. The semiconductor memory device according to claim 12, wherein the value of VH−

Vh+Vl is larger than VL and the value of VL+Vh−

Vl is smaller than VH.

14. The semiconductor memory device according to claim 12, wherein a value of Vh−

VH is equal to or smaller than a value of VH−

VL and a value of Vl−

VL is equal to or smaller than a value of VH−

VL.

15. The semiconductor memory device according to claim 12, wherein a value of VH−

VL is smaller than a withstand voltage of said latch circuit.

16. The semiconductor memory device according to claim 12, further comprising a plurality of third inverting elements generating the voltage Vh and Vl.

17. The semiconductor memory device according to claim 16, wherein a value of Vh−

Vl is smaller than a withstand voltage of said third inverting element.

18. The semiconductor memory device according to claim 12, wherein Vh represents a potential of said semiconductor substrate at a time of an erase operation.

19. The semiconductor memory device according to claim 12, wherein VL represents a potential on said word line at a time of an erase operation.

20. The semiconductor memory device according to claim 12, wherein VH is equal to Vl.

21. The semiconductor memory device according to claim 10, further comprising,

a second level shifter having a second latch circuit, a third capacitor and a fourth capacitor,

said second latch circuit having a third node and a fourth node set to a third voltage or a fourth voltage, said fourth node being set to said fourth voltage when said third node is set to said third voltage and said fourth node being set to said third voltage when said third node is set to said fourth voltage,

said third capacitor having a fifth terminal and a sixth terminal and said fifth terminal of said third capacitor being connected to said third node,

said fourth capacitor having a seventh terminal and an eighth terminal and said seventh terminal of said fourth capacitor being connected to said fourth node; and

a first switch circuit supplying said negative voltage to said word line in accordance with an output of said second level shifter.

22. The semiconductor memory device according to claim 21, further comprising,

a third level shifter having a third latch circuit, a fifth capacitor and a sixth capacitor,

said third latch circuit having a fifth node and a sixth node set to a fifth voltage or a sixth voltage, said sixth node being set to said sixth voltage when said fifth node is set to said fifth voltage and said sixth node being set to said fifth voltage when said fifth node is set to said sixth voltage,

said fifth capacitor having a ninth terminal and a tenth terminal, said ninth terminal of said fifth capacitor being connected to said fifth node,

said sixth capacitor having an eleventh terminal and a twelfth terminal and said eleventh terminal of said sixth capacitor being connected to said sixth node;

and

a second switch circuit supplying a predetermined voltage to said word line in accordance with an output of said third level shifter.

23. The semiconductor memory device according to claim 10, further comprising a resetting transistor initializing a potential on said first node and a potential on said second node.