Multi-processor type storage control apparatus for performing access control through selector

• US 6,601,134 B1
• Filed: 04/26/1999
• Issued: 07/29/2003
• Est. Priority Date: 04/27/1998
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Fujimoto, Kazuhisa, Yamagami, Kenji, Honma, Hisao, Kurosu, Yasuo
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Encarnacion, Yamir
• Application Number:
  US09/298,967
• Time in Patent Office: 1,555 Days
• Field of Search: 711/111, 711/112, 711/113, 711/114, 711/118, 714/519, 714/819, 714/820, 714/821
• US Class Current: 711/111
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cache memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

Claims

1. A storage control apparatus coupled to a central processing unit and a storage unit, wherein said storage control apparatus is configured to control input/output of data between said control processing unit and said storage unit, said storage control apparatus comprising:

at least two processors coupled to said central processing unit and said storage unit;

a cache memory unit for temporarily storing data of said storage unit;

a shared memory unit for storing information concerning control of said cache memory unit and said storage unit; and

a selector coupled to each of said at least two processors, said cache memory unit and said shared memory unit through access paths to selectively apply access requests from said at least two processors to said cache memory unit and said shared memory unit,

wherein said shared memory unit includes a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and each shared memory section having an access circuit;

wherein said selector controls said access requests based on said information, receives an address, a write command and write data from one of said two processors which performs a write process to said shared memory unit, and transmits said address, write command and write data to each of said shared memory sections;

wherein said access circuit of said shared memory section serving as master receives said address, write command and write data from said selector and sends said write data and said received address to said shared memory section serving as slave through said inter-shared memory path; and

wherein said access circuit of said shared memory section serving as slave writes said write data received through said inter-shared memory path to a location which is indicated by said address received through said inter-shared memory path.

2. A storage control unit according to claim 1,

wherein said access circuit of said shared memory section serving as slave compares said address received through said inter-shared memory path with said address from said selector and writes said write data from said selector to a location which is indicated by said address received through said inter-shared memory path when said addresses coincide with each other.

3. A storage control apparatus coupled to a central processing unit and a storage unit, wherein said storage control apparatus is configured to control input/output of data between said control processing unit and said storage unit, said storage control apparatus comprising:

at least two processors coupled to said central processing unit and said storage unit;

a cache memory unit for temporarily storing data of said storage unit;

a shared memory unit for storing information concerning control of said cache memory unit and said storage unit; and

a selector coupled to each of said at least two processors, said cache memory unit and said shared memory unit through access paths to selectively apply access requests from said at least two processors to said cache memory unit and said shared memory unit,

wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and each shared memory section having an access circuit;

wherein said selector controls said access requests based on said information, receives an address and a read command from one of said two processors when said one processor performs a read process to said shared memory unit, and transmits said address and read command to each of said two shared memory sections;

wherein said access circuit of said shared memory section serving as master receives said address and read command from said selector, reads data from a location indicated by said address to transfer it to said selector, and transmits said address to said shared memory section serving as slave through said inter-shared memory path;

wherein said access circuit of said shared memory section serving as slave reads out data from a location which is indicated by said address received through said inter-shared memory path and transfers the read-out data to said selector; and

wherein said selector compares the read data received from said shared memory section serving as master with the read data received from said shared memory section serving as slave and, when both said data coincide with each other, transmits said coincidental read data to one of said two processors.

4. A storage control apparatus according to claim 3,

wherein said access circuit of said shared memory section serving as slave compares said address received through said inter-shared memory path with said address from said selector, reads out data from a location indicated by said address received through said inter-shared memory path, and transfers the read data to said selector when both said addresses coincide with each other.

5. A storage control apparatus coupled to a central processing unit and a storage unit, wherein said storage control apparatus is configured to control input/output of data between said control processing unit and said storage unit, said storage control apparatus comprising:

at least two processors coupled to said central processing unit and said storage unit;

a cache memory unit for temporarily storing data of said storage unit;

a shared memory unit for storing information concerning control of said cache memory unit and said storage unit; and

a selector coupled to each of said at least two processors, said cache memory unit and said shared memory unit through access paths to selectively apply access requests from said at least two processors to said cache memory unit and said shared memory unit,

wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and each shared memory section having an access circuit;

wherein said selector controls said access requests based on said information, receives an address, a write command and write data from one of said two processors when said one processor performs a write process to said shared memory unit, and transmits said address, said write command and said write data to said shared memory section serving as master;

wherein said access circuit of said shared memory section serving as master writes said write data to a location indicated by said address in response to said write command from said selector and transmits said address, write command and write data to said shared memory section serving as slave through said inter-shared memory path; and

wherein said access circuit of said shared memory section serving as slave writes said write data received through said inter-shared memory path to a location indicated by said address received through said inter-shared memory path and transmits a write end report to said shared memory section serving as master through said inter-shared memory path.

6. A storage control apparatus coupled to a central processing unit and a storage unit, wherein said storage control apparatus is configured to control input/output of data between said control processing unit and said storage unit, said storage control apparatus comprising:

at least two processors coupled to said central processing unit and said storage unit;

a cache memory unit for temporarily storing data of said storage unit;

a shared memory unit for storing information concerning control of said cache memory unit and said storage unit; and

a selector coupled to each of said at least two processors, said cache memory unit and said shared memory unit through access paths to selectively apply access requests from said at least two processors to said cache memory unit and said shared memory unit,

wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and each shared memory section having an access circuit;

wherein said selector controls said access requests based on said information, receives an address and a read command from one of said two processors when said one processor performs a read process of said shared memory unit, and transmits said address and read command to said shared memory section serving as master;

wherein said access circuit of said shared memory section serving as master reads out data from a location indicated by said address in response to said read command from said selector, and transmits said address and said read command to said shared memory section serving as slave through said inter-shared memory path;

wherein said access circuit of said shared memory section serving as slave reads out data from a location indicated by said address received through said inter-shared memory path in response to said read command received through said inter-shared memory path, and transfers the read-out data to said shared memory section serving as master through said inter-shared memory path,

wherein said access circuit of said shared memory section serving as master compares the read data read out of said shared memory section serving as master with the read data received from said shared memory section serving as slave, and transmits said read data and a read-out end report to said selector when both the read data coincide with each other.