Method and apparatus for increasing computer performance through asynchronous memory block initialization
First Claim
1. A method for increasing processing performance in a computer system having at least one instruction processor to process instructions of an instruction stream, and having a memory to store data, the method comprising:
- identifying one or more inactive data blocks in the memory;
generating a list of addresses corresponding to the identified inactive data blocks;
identifying available computing cycles during processing in the computer system; and
initializing, via the at least one instruction processor that is used to process instructions of the instruction stream, the one or more inactive data blocks associated with the list of addresses to a predetermined state during one or more of the available computing cycles, wherein the initializing is performed asynchronously with respect to processing of the instruction stream by the at least one instruction processor.
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Abstract
A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.
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Citations
37 Claims
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1. A method for increasing processing performance in a computer system having at least one instruction processor to process instructions of an instruction stream, and having a memory to store data, the method comprising:
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identifying one or more inactive data blocks in the memory;
generating a list of addresses corresponding to the identified inactive data blocks;
identifying available computing cycles during processing in the computer system; and
initializing, via the at least one instruction processor that is used to process instructions of the instruction stream, the one or more inactive data blocks associated with the list of addresses to a predetermined state during one or more of the available computing cycles, wherein the initializing is performed asynchronously with respect to processing of the instruction stream by the at least one instruction processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method for increasing processing performance in a computer system having at least one instruction processor to process instructions of an instruction stream, and having a memory to store data, the method comprising:
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identifying one or more inactive data pages in the memory;
storing a first list of first addresses corresponding to the identified inactive data pages in a first linked list;
identifying idle memory write cycles associated with a data write interface between the instruction processor and the memory;
clearing the one or more inactive data pages associated with the list of addresses to a predetermined state during one or more of the identified idle memory write cycles, wherein the at least one instruction processor that processes instructions of the instruction stream initiates the clearing via the data write interface independent of activity in the instruction stream; and
storing a second list of second addresses corresponding to the one or more inactive data pages that have been cleared in a second linked list. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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32. A system for asynchronously initializing inactive data blocks in a computing system, comprising:
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a memory for storing instructions and data associated with an instruction stream, wherein the memory includes inactive data blocks currently unused by the computing system and having residual data therein;
a first queue to store one or more addresses corresponding to the inactive data blocks;
a second queue to store one or more addresses corresponding to the inactive data blocks that have been initialized; and
at least one instruction processor to process instructions of the instruction stream, the at least one instruction processor including a write interface coupled to the memory to allow data to be written to the memory, wherein the at least one instruction processor is configured and arranged to accept the addresses from the first queue, initialize the corresponding inactive data blocks via the write interface during idle memory write cycles between the at least one instruction processor and the memory, and to store the addresses corresponding to the inactive data blocks that have been initialized onto the second queue. - View Dependent Claims (33, 34, 35, 36)
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37. A system for asynchronously initializing inactive data blocks in a computing system, comprising:
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a memory for storing instructions and data associated with an instruction stream, wherein the memory includes inactive data blocks currently unused by the computing system and having residual data therein, and wherein the memory further includes a first linked list to store one or more addresses corresponding to the inactive data blocks and a second linked list to store one or more addresses corresponding to the inactive data blocks that have been initialized; and
at least one instruction processor to process instructions of the instruction stream, the at least one instruction processor including a write interface coupled to the memory to allow data to be written to the memory, wherein the at least one instruction processor is configured and arranged to accept the addresses from the first linked list, initialize the corresponding inactive data blocks via the write interface during idle memory write cycles between the at least one instruction processor and the memory, and to store the addresses corresponding to the inactive data blocks that have been initialized onto the second linked list.
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Specification