Continuous interleave burst access

• US 6,601,156 B2
• Filed: 04/08/2002
• Issued: 07/29/2003
• Est. Priority Date: 07/03/1996
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Blodgett, Greg A.
• Primary Examiner(s): Portka, Gary J
• Application Number:
  US10/118,299
• Publication Number:
  US 20020152350A1
• Time in Patent Office: 477 Days
• Field of Search: 365/233, 711/105, 711/137, 711/168, 711/169, 711/204, 711/213, 711/217, 711/218
• US Class Current: 711/213
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

Claims

1. A synchronous memory device, comprising:

addressable memory cells;

a memory controller coupled to the memory cells; and

an external output connection coupled to the addressable memory cells,

wherein, in response to a first externally-provided start address, the memory controller is adapted to provide a first data series from the memory cell array to the external output connection and to produce an anticipated start address to provide an anticipated data series from the memory cell array to the external output connection, and

wherein the anticipated data series follows the first data series to maintain an active data output stream.

2. The synchronous memory device of claim 1, further comprising address counter circuitry coupled to the controller and adapted to generate an interleaved sequence of memory cell addresses in response to the first externally-provided start address and the anticipated start address.

3. The synchronous memory device of claim 1, further comprising address counter circuitry coupled to the controller and adapted to generate a linear sequence of memory cell addresses in response to the first externally-provided start address and the anticipated start address.

4. The synchronous memory device of claim 1, wherein the controller includes an address generator circuit for producing the anticipated start address.

5. The synchronous memory device of claim 1, further comprising a comparator circuit coupled to the controller adapted to compare the anticipated start address and a second externally-provided start address.

6. The synchronous memory device of claim 1, wherein the controller includes a comparator circuit adapted to compare the anticipated start address and a second externally-provided start address.

7. A synchronous memory device, comprising:

a memory cell array;

address circuitry coupled to the memory cell array;

control circuitry coupled to the address circuitry and to the memory cell array; and

an external output connection coupled to the memory cell array,

wherein the control circuitry is adapted to provide a first burst output from the memory cell array to the external output connection in response to a first externally-provided start address,

wherein the control circuitry is adapted to internally provide a start address in response to the first externally-provided initial start address and in anticipation of a second externally-provided start address,

wherein, in response to the internally provided start address, the control circuitry is adapted to initiate an anticipated burst output from the memory cell array to the external output connection, and

wherein the anticipated burst output follows the first burst output and maintains an active data output stream on the external output connection for the first externally-provided start address and the second externally-provided start address.

8. The synchronous memory device of claim 7, further comprising address counter circuitry coupled to the control circuitry and adapted to generate an interleaved sequence of memory cell addresses in response to the first externally-provided start address and the internally-provided start address.

9. The synchronous memory device of claim 7, further comprising address counter circuitry coupled to the control circuitry and adapted to generate a linear sequence of memory cell addresses in response to the first externally-provided start address and the internally-provided start address.

10. The synchronous memory device of claim 7, wherein the control circuitry includes an address generator circuit for producing the anticipated start address.

11. The synchronous memory device of claim 7, further comprising a comparator circuit coupled to the control circuitry and adapted to compare the anticipated start address and a second externally-provided start address.

12. The synchronous memory device of claim 7, wherein the control circuitry includes a comparator circuit adapted to compare the anticipated start address and a second externally-provided start address.

13. A synchronous memory device, comprising:

addressable memory cells;

a memory controller coupled to the memory cells; and

an external output connection coupled to the addressable memory cells,

wherein the memory controller is adapted to output a data series from the addressable memory cells to the external output connection in response to external read requests beginning with a start address contained within the external read requests,

wherein the memory controller is adapted to output a first data series to the external output connection in response to a first external read request beginning with a first start address contained within the first external read request,

wherein, in response to the first start address, the memory controller is adapted to output an anticipated data series to the external output connection beginning with an anticipated start address in anticipation of a second external read request,

wherein, in response to the second external read request beginning with a second start address, the memory controller is adapted to continue to output the anticipated data series as a second data series when the second start address is the same as the anticipated start address, and

wherein the second data series follows the first data series to maintain an active data output stream on the external output connection.

14. The synchronous memory device of claim 13, further comprising address counter circuitry coupled to the memory controller and adapted to generate an interleaved sequence of memory cell addresses in response to the first start address and the anticipated start address.

15. The synchronous memory device of claim 13, further comprising address counter circuitry coupled to the memory controller and adapted to generate a linear sequence of memory cell addresses in response to the first start address and the anticipated start address.

16. The synchronous memory device of claim 13, wherein the memory controller includes an address generator circuit for producing the anticipated start address.

17. The synchronous memory device of claim 13, further comprising a comparator circuit coupled to the memory controller adapted to compare the anticipated start address and a second externally-provided start address.

18. The synchronous memory device of claim 13, wherein the memory controller includes a comparator circuit adapted to compare the anticipated start address and the second start address.

19. A system comprising:

a microprocessor; and

a synchronous memory device, including;

addressable memory cells coupled to the microprocessor; and

a memory controller coupled to the memory cells and to the microprocessor;

wherein the microprocessor is adapted to provide a first start address to provide a first data series from the synchronous memory device,

wherein, in response to the first start address provided by the microprocessor, the memory controller is adapted to produce an anticipated start address to provide an anticipated data series from the synchronous memory device in anticipation of a second start address from the microprocessor and a corresponding second data series from the synchronous memory device, and

wherein the anticipated data series follows the first data series to maintain an active data output stream from the first data series to the second data series.

20. The system of claim 19, wherein the second start address from the microprocessor and the anticipated start address are the same.

21. The system of claim 19, wherein the memory controller includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

22. The system of claim 19, wherein the synchronous memory device further includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

23. The system of claim 19, wherein the second start address is produced using an interleaved sequence.

24. The system of claim 19, wherein the second start address is produced using a linear sequence.

25. The system of claim 19, wherein the microprocessor withholds the second start address if the second start address and the anticipated start address are the same.

26. The system of claim 19, wherein the synchronous memory device is a burst extended data out dynamic random access memory (BEDO DRAM).

27. A system, comprising:

a microprocessor; and

a synchronous memory device, including;

a memory cell array;

address circuitry coupled to the memory cell array; and

control circuitry coupled to the address circuitry and to the memory cell array,

wherein the microprocessor is adapted to provide a first start address to the synchronous memory device;

wherein the control circuitry is adapted to provide a first burst output from the memory cell array to the microprocessor in response to the first start address,

wherein the control circuitry is adapted to provide an anticipated start address in response to the first start address in anticipation of a second start address from the microprocessor,

wherein, in response to the anticipated start address, the control circuitry is adapted to initiate an anticipated burst output from the memory cell array, and

wherein the anticipated burst output follows the first burst output and maintains an active data output stream to the microprocessor for the first externally-provided start address and the second externally-provided start address.

28. The system of claim 27, wherein the second start address from the microprocessor and the anticipated start address are the same.

29. The system of claim 27, wherein the control circuitry includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

30. The system of claim 27, wherein the synchronous memory device further includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

31. The system of claim 27, wherein the second start address is produced using an interleaved sequence.

32. The system of claim 27, wherein the second start address is produced using a linear sequence.

33. The system of claim 27, wherein the microprocessor withholds the second start address if the second start address and the anticipated start address are the same.

34. The system of claim 27, wherein the synchronous memory device is a burst extended data out dynamic random access memory (BEDO DRAM).

35. A system, comprising:

a microprocessor; and

a synchronous memory device, including;

addressable memory cells; and

a memory controller coupled to the memory cells,

wherein the microprocessor is adapted to provide read requests to the synchronous memory device,

wherein the memory controller is adapted to output a data series from the addressable memory cells to the microprocessor in response to the read requests beginning with a start address contained within the read requests,

wherein the memory controller is adapted to output a first data series to the microprocessor in response to a first external read request beginning with a first start address contained within the first external read request,

wherein, in response to the first start address, the memory controller is adapted to initiate an output of an anticipated data series to the microprocessor beginning with an anticipated start address in anticipation of a second read request from the microprocessor,

wherein, in response to the second read request from the microprocessor that begins with a second start address, the memory controller is adapted to compare the second start address to the anticipated start address and to continue to output the anticipated data series as a second data series when the second start address is the same as the anticipated start address, and

wherein the second data series follows the first data series to maintain an active data output stream on the external output connection.

36. The system of claim 35, wherein the second start address and the anticipated start address are the same.

37. The system of claim 35, wherein the memory controller includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

38. The system of claim 35, wherein the synchronous memory device further includes a comparator circuit adapted to compare the second start address and the anticipated cell address and to produce an output in response thereto.

39. The system of claim 35, wherein the second start address is produced using an interleaved sequence.

40. The system of claim 35, wherein the second start address is produced using a linear sequence.

41. The system of claim 35, wherein the microprocessor withholds the second start address if the second start address and the anticipated start address are the same.

42. The system of claim 35, wherein the synchronous memory device is a burst extended data out dynamic random access memory (BEDO DRAM).

43. A system, comprising:

a burst access memory, including;

memory cells; and

address generation circuitry coupled to the memory cells; and

a microprocessor coupled to the memory cells and to the address generation circuitry,

wherein the microprocessor is adapted to produce read requests for data stored in the memory cells,

wherein each read request includes a start memory cell address,

wherein, in response to a first start memory cell address from a first read request, the address generation circuitry is adapted to produce an anticipated start memory cell address in anticipation of a second read request from the microprocessor,

wherein the burst access memory is adapted to provide a first data series in response to the first start memory cell address and an anticipated data series in response to the anticipated start memory cell address, and

wherein the anticipated data series follows the first data series to maintain an active data output stream.

44. The system of claim 43, wherein the burst access memory includes a comparator circuit adapted to compare the anticipated start memory cell address and a second start memory cell address provided by the microprocessor as part of the second read request.

45. The system of claim 43, wherein the microprocessor withholds the second read request if the anticipated start memory cell address is equal to a second start memory cell address provided by the microprocessor as part of the second read request.

46. The system of claim 43, wherein the burst access memory includes fall page length column sequence circuitry for outputting data stored at each column of a page of memory.

47. A method for continuously outputting data from a synchronous memory device, the method comprising:

providing a first read request from a microprocessor, the first read request including a first memory cell start address for the synchronous memory device;

in response to the first read request, initiating a read operation using a memory controller provided in the synchronous memory device to output a first data series from the synchronous memory device;

in response to the first memory cell start address and in anticipation of a second read request from the microprocessor, generating an anticipated memory cell start address using the memory controller provided in the synchronous memory device;

initiating an anticipated read operation using the anticipated memory cell start address; and

outputting an anticipated second data series from the synchronous memory device starting at the anticipated memory cell start address such that the anticipated data series follows the first data series to maintain an active data output stream between the first read request and the second read request from the microprocessor.

48. The method of claim 47, further including outputting a full column data sequence from the synchronous memory device.

49. The method of claim 47, further including withholding the second read request from the microprocessor if the anticipated memory cell start address is the same as a second memory cell start address for the second read request.

50. The method of claim 47, wherein the anticipated memory cell start address is generated using an interleaved sequence.

51. The method of claim 47, wherein the anticipated memory cell start address is generated using a linear sequence.

52. The method of claim 47, further including:

providing the second read request from the microprocessor, the second read request including a second memory cell start address, the second memory cell start address being different than the new memory cell start address; and

initiating a second read operation and outputting data from the synchronous memory device starting at the second memory cell start address.

53. A method for continuously outputting data from a synchronous memory device, the method comprising:

providing a first read request from a microprocessor for a first data series, the first read request including a first memory cell start address for the synchronous memory device;

in response to the first read request, initiating a read operation using a memory controller provided in the synchronous memory device to output the first data series from the synchronous memory device;

in response to the first memory cell start address and in anticipation of a second read request from the microprocessor for a second data series, generating an anticipated memory cell start address using the memory controller provided in the synchronous memory device;

initiating an anticipated read operation using the anticipated memory cell start address;

outputting an anticipated second data series from the synchronous memory device starting at the anticipated memory cell start address;

providing the second read request from the microprocessor for the second data series, the second read request including a second memory cell start address for the synchronous memory device;

comparing the second memory cell start address to the anticipated memory cell start address; and

upon determining that the second memory cell start address is the same as the anticipated memory cell start address, continuing to output the anticipated second data series as the second data series such that the second data series follows the first data series to maintain an active data output stream between the first read request and the second read request from the microprocessor.

54. The method of claim 53, further including outputting a full column data sequence from the synchronous memory device.

55. The method of claim 53, wherein continuing to output the anticipated second data series as the second data series includes withholding the second read request if the anticipated memory cell start address is the same as the second memory cell start address for the second read request.

56. The method of claim 53, wherein the anticipated memory cell start address is generated using an interleaved sequence.

57. The method of claim 53, wherein the anticipated memory cell start address is generated using a linear sequence.

58. The method of claim 53, further including, upon determining that the second memory cell start address is different than the anticipated memory cell start address, outputting the second data series from the synchronous memory device starting at the second memory cell start address.