Count/address generation circuitry

• US 6,601,158 B1
• Filed: 12/30/1999
• Issued: 07/29/2003
• Est. Priority Date: 12/30/1999
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Shahri, Homayoun, Abbott, Curtis
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/475,647
• Time in Patent Office: 1,307 Days
• Field of Search: 711/200-220, 711/221, 365/236
• US Class Current: 711/220
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3552 using wraparound, e.g. modulo or circular addressing

Abstract

According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.

Claims

1. An apparatus comprising:

a first and second counter both including a count computation circuit and an upper bound circuit, the output of the upper bound circuit of the first counter coupled to the count computation circuit of the second counter;

a lookup table addressed by a current count value of the first counter; and

a combining circuit coupled to the output of the lookup table and to receive a current count value of the second counter.

2. The apparatus of claim 1, wherein the count computation circuit of the first counter one of increments and decrements the current count value by a fixed value.

3. The apparatus of claim 1, wherein the count computation circuit of the second counter one of increments and decrements the current count value by one of a selectable and a variable value.

4. The apparatus of claim 3, wherein the count computation circuit of the second counter includes a count computation value register to store the variable value.

5. The apparatus of claim 1, wherein the output of the upper bound circuit of the first counter is also coupled to the upper bound circuit of the second counter.

6. The apparatus of claim 1, wherein the first and second counter both include an initial count value circuit that provides one of a selectable and a variable value.

7. The apparatus of claim 1, wherein at least part of the lookup table is dynamic memory.

8. The apparatus of claim 1, further comprising logic coupled between the first counter and the lookup table to receive the current count value of the first counter, the logic also coupled to receive a different input, the logic to provide addresses to the lookup table based on the current count value of the first counter and the different input.

9. The apparatus of claim 1, wherein the combining circuit adds.

10. The apparatus of claim 1, wherein the combining circuit performs an exclusive OR operation.

11. The apparatus of claim 1, the lookup table to store separate pluralities of extension values, each separate plurality of extension values being stored such that it will be sequentially addressed by the first counter.

12. The apparatus of claim 11, wherein the first counter includes an initial count value circuit that includes an initial count value register, the contents of which select between the separate pluralities of extension values.

13. The apparatus of claim 11, wherein each of the pluralities of extension value allows the output of the combining circuit to provide an output consistent with a different multi-sequence generator.

14. The apparatus of claim 11, wherein a first of the pluralities of extension values provides for bit reversed addressing.

15. The apparatus of claim 11, wherein a first of the pluralities of extension values is a predictable sequence of nonsequential values of which at least some are not fixed distances apart.

16. An apparatus comprising:

a plurality of circuits each including,

two counters, with limit registers, connected sequentially to respectively provide an extension and base count value,

a lookup table coupled to be addressed at least in part by the extension count value, and

a combining circuit coupled to the output of the lookup table and to receive the base count value.

17. The apparatus of claim 16, further comprising a loading circuit coupled to load initial count values into at least one of the two counters of a first of the plurality of circuits with the output of a second of the plurality of circuits.

18. The apparatus of claim 16, wherein at least part of the lookup table is dynamic memory.

19. The apparatus of claim 16, wherein the combining circuit adds.

20. The apparatus of claim 16, the lookup table to store separate pluralities of extension values, each separate plurality of extension values being stored such that it will be sequentially addressed.

21. The apparatus of claim 20, wherein the counter of a given one of the plurality of circuits that provides the extension count value can be set to different initial count values to select between the separate pluralities of extension values.

22. The apparatus of claim 20, wherein each of the pluralities of extension values allows the output of the combining circuit to provide an output consistent with a different multi-sequence generator.

23. The apparatus of claim 20, wherein a first of the pluralities of extension values provides for bit reversed addressing.

24. The apparatus of claim 20, wherein a first of the pluralities of extension values is a predictable sequence of nonsequential values of which at least some are not fixed distances apart.

25. A programmable core comprising:

an input array to receive data and control signals;

a set of one or more register files coupled to said input array to receive said data;

a set of one or more datapaths coupled to said set of one or more register files to operate on said data;

a plurality of count/address generators each having a lookup table to provide predictable sequences of addresses at address ports of said set of one or more register files; and

control logic coupled to receive said control signals and coupled to control said set of one or more datapaths and said plurality of count/address generators.

26. The programmable core of claim 25, wherein said control logic is preprogrammed before execution of a program such that all instructions of the program are stored in the core.

27. The programmable core of claim 25, wherein said control logic comprising a loading circuit coupled to load initial count values into at least a first of said plurality of count/address generators with the output or other values of a second of the plurality of count/address generators.

28. The programmable core of claim 27, wherein a first and second of said plurality of count/address generators each contains two counters that respectively provide an extension and base count value, and one of said other values is the loading of the current base count value of the first count/address generator into the current base count value of the second count/address generator.

29. The programmable core of claim 25, wherein said control logic comprising a storing circuit coupled to store at least certain of the state of one of said plurality of count/address generators in one of said set of register files.

30. The programmable core of claim 25, wherein each of said plurality of count/address generators includes:

a first and second counter both including a count computation circuit and an upper bound circuit, the output of the upper bound circuit of the first counter coupled to the count computation circuit and upper bound circuit of the second counter;

a lookup table addressed by the current count value of the first counter; and

a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.