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System and method for fast interconnect delay estimation through iterative refinement

  • US 6,601,223 B1
  • Filed: 09/29/2000
  • Issued: 07/29/2003
  • Est. Priority Date: 09/29/2000
  • Status: Active Grant
First Claim
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1. A method for estimating the interconnect delay times in an integrated circuit using a resistor-capacitor (RC) tree model, comprising the steps of:

  • a) initializing an effective capacitance for each RC tree node;

    b) initializing a delay on each RC tree segment;

    c) computing slew at a source node of the RC tree, using an effective capacitance last calculated for the source node;

    d) computing remaining slews for each node in the RC tree by propagating outward to sinks from the source;

    e) recomputing effective capacitances for each RC tree node by propagating inward to the source node from the sinks;

    f) updating the delay of each RC tree segment using effective capacitances recomputed in step (e);

    g) recomputing the source node slew using an effective capacitance recomputed in step (e); and

    h) repeating steps (d) to (h) until the source node slew computed at step (c) is within a specified threshold from the source node slew recomputed at step (g).

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