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Tightloop method of timing driven placement

  • US 6,601,226 B1
  • Filed: 03/14/2000
  • Issued: 07/29/2003
  • Est. Priority Date: 03/14/2000
  • Status: Active Grant
First Claim
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1. A method of placing cells for an integrated circuit design, comprising the steps of:

  • a) initially placing cells at particular locations;

    b) estimating a plurality of capacitances associated with a plurality of nets corresponding to the current x-y position of cell placements;

    c) performing a timing analysis based on the plurality of capacitances;

    d) determining a plurality of net weights as a function of the timing analysis, an overlap, and a net length;

    e) determining a plurality of dampened net weights, wherein each dampened net weight is equal to a corresponding one of the plurality of net weights multiplied by a first weight factor, plus a corresponding previous one of the plurality of dampened net weights multiplied by one minus the first weight factor;

    f) changing the cell placements according to the plurality of dampened net weights; and

    g) repeating one or more of the steps b-f iteratively a plurality of times.

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