Manufacture of integrated fluidic devices

• US 6,602,791 B2
• Filed: 04/27/2001
• Issued: 08/05/2003
• Est. Priority Date: 04/27/2001
• Status: Expired due to Term

• Current Assignee: Teledyne Digital Imaging, Inc. (Teledyne Technologies Incorporated)
• Original Assignee: Dalsa Semiconductor Inc (Teledyne Technologies Incorporated)
• Inventors: Ouellet, Luc, Tyler, Heather
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): DEO, DUY VU NGUYEN
• Application Number:
  US09/842,836
• Publication Number:
  US 20020160561A1
• Time in Patent Office: 830 Days
• Field of Search: 438/52, 438/696, 438/700, 438/703, 438/735, 438/720, 438/723, 438/724, 438/756, 257/734, 257/735, 216/2, 216/11, 216/17, 216/41, 216/51, 216/78, 216/79
• US Class Current: 438/696
• CPC Class Codes: B01L 2200/12 Specific details about manufacturing devices
• CPC Class Codes: B01L 2300/0645 Electrodes
• CPC Class Codes: B01L 2400/0415 electrical forces, e.g. electrokinetic
• CPC Class Codes: B01L 3/502707 characterised by the manufacture of the container or its components by shaping or joining plastic parts B29C59/00, B29C65/00; by laminating B32B37/00; manufacture of microstructural devices in general B81C

Abstract

In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.

Claims

1. A method of fabricating a microstructure for microfluidics applications, comprising the steps of:

forming a first layer of etchable material on a suitable substrate;

forming a mechanically stable support layer over said etchable material;

applying a mask over said support layer to expose at least one opening in said mask;

performing at anistropic etch through each said opening to create a bore extending through said support layer to said layer of etchable material;

performing an isotropic etch through each said bore to form a microchannel in said etchable material extending under said support layer;

forming a further layer of depositable material over said support layer until portions of said depositable layer overhanging each said opening meet and thereby close the microchannel formed under each said opening; and

wherein a first sacrificial layer is deposited under said support layer, a second sacrificial layer is deposited on top of said support layer, and each said sacrificial layer is removed by etching at least in the vicinity of said microchannel after formation thereof.

2. A method as claimed in claim 1, wherein said further layer is of the same material as said first layer of etchable material.

3. A method as claimed in claim 2, wherein said etchable material is SiO₂.

4. A method as claimed in claim 3, wherein said support layer is made of Si₃N₄.

5. A method as claimed in claim 1, wherein said first layer is deposited by PECVD.

6. A method as claimed in claim 5, wherein said first layer is about 10 μ

m thick.

7. A method as claimed in claim 1, wherein each said sacrificial layer is TiN.

8. A method as claimed in claim 7, wherein each said sacrificial layer is formed by collimated reactive physical vapour deposition (CRPVD).

9. A method as claimed in claim 8, wherein said anisotropic etch through said support layer is a reactive ion anisotropic etch.

10. A method as claimed in claim 9, wherein an anisoptropic etch is performed on said microstructure through said etchable material to define a MEMS region containing said microchannel.

11. A method as claimed in claim 1, wherein after etching said bore an additional layer is deposited over said support layer so as to extend into said bore covering sidewalls and a bottom thereof, and a portion of said additional layer covering said bottom of said bore is etched away to leave sidewall spacers in said bore through which said isotropic etch is performed in order to form said microchannel.

12. A method as claimed in claim 11, wherein said additional layer is TiN.

13. A method as claimed in claim 12, wherein said additional layer is deposited by CRPVD.

14. A method as claimed in claim 1, wherein said substrate includes CMOS circuitry.

15. A method as claimed in claim 1, wherein said first layer is deposited over a conductive layer forming a lower electrode.

16. A method as claimed in claim 15, wherein said conductive layer is polysilicon.

17. A method as claimed in claim 16, wherein a protective layer is formed between said conductive layer and said first layer.

18. A method as claimed in claim 17, wherein said protective layer is Si₃N₄.

19. A method as claimed in claim 18, wherein a further conductive layer is formed over said protective layer.

20. A method as claimed in claim 19, wherein said further conductive layer is TiN.

21. A method as claimed in claim 1, wherein said further conductive layer is formed by CRPVD.

22. A method as claimed in claim 21, wherein said further conductive layer is deposited at about 400°

C.

23. A method as claimed in claim 1, wherein after forming said further layer, an etch step is performed to remove said further layer from said supporting layer except in the region of said opening, and then a conductive layer is deposited to provide an upper electrode.

24. A method as claimed in claim 23, wherein said conductive layer comprises PVD Ti/TiN/al/Tin sublayers.

25. A method as claimed in claim 24, wherein an anisotropic etch is performed on said sublayers to define electrodes and interconnects for said microstructure.

26. A method as claimed in claim 25, wherein said steps are carried out at a temperature not exceeding 450°

C.

27. A method of fabricating a microstructure for microfluidics applications, comprising:

providing a substrate containing CMOS circuitry having an upper conductive layer;

forming a protective layer on said upper conductive layer;

forming a first sacrificial layer on said protective layer;

forming a first layer of etchable material on said protective layer;

depositing a second sacrificial layer on said first layer;

depositing a mechanically stable support layer on said second sacrificial layer;

applying a mask over said support layer to expose at least one opening in said mask;

performing an anistropic etch through the said opening to create a bore extending through said support layer to said layer of etchable material;

performing an isotropic etch through each said bore to form a microchannel in said etchable material extending under said support layer; and

forming a further layer of depositable material aver said support layer until portions of said depositable layer overhanging each said opening meet and thereby close the microchannel formed under each said opening;

removing said depositable material in regions not over said opening;

and depositing a conductive layer over said depositable material to form an upper electrode.

28. A method as claimed in claim 27, further comprising depositing a third sacrificial layer over said support layer.

29. A method as claimed in claim 28, wherein said sacrificial layers are TiN.

30. A method as claimed in claim 29, wherein said sacrificial layers are deposited by collimated reactive physical vapour deposition (CRPVD).

31. A method as claimed in claim 30, wherein said first layer is SiO₂.

32. A method as claimed in claim 31, wherein said first layer is deposited by PECVD.

33. A method as claimed in claim 32, wherein said first layer is about 10 μ

m thick.

34. A method as claimed in claim 27, wherein after performing said anisotropic etch to create said bore, a further sacrificial layer is deposited to extend into said bore, and a bottom portion of said sacrificial layer is etched away to leave sidewall spacers in said bore while said isotropic etch is performed to form said microchannel.

35. A method as claimed in claim 27, wherein said process steps are carried out at temperature not exceeding 450°

C.

36. A method as claimed in claim 34, wherein said further sacrificial layer is TiN.

37. A method of fabricating a fluidic device, comprising the steps of:

providing a layer of etchable material;

depositing a first sacrificial layer over said layer of etchable material;

forming a protective layer over said first sacrificial layer;

depositing a second sacrificial layer over said protective layer;

providing at least one opening in said protective layer and said first and second sacrificial layers;

etching a cavity in said etchable layer through said at least one opening;

etching away said first and second sacrificial layers at least in the vicinity of said cavity;

depositing a further layer over said protective layer such that portions thereof overhang said at least one opening, said overhanging portions meeting to close said opening and thereby form a closed microchannel within said etchable layer.

38. A method as claimed in claim 37, wherein said etchable material is SiO₂.

39. A method as claimed in claim 38, wherein said further layer is SiO₂.

40. A method as claimed in claim 39, wherein said protective layer is Si₃N₄.

41. A method as claimed in claim 37, wherein said opening is protected with sidewall spacers during said etching of said cavity.

42. A method as claimed in claim 41, wherein said spacers are TiN.