High temperature circuit apparatus

• US 6,603,145 B2
• Filed: 05/02/2002
• Issued: 08/05/2003
• Est. Priority Date: 03/07/2000
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Balch, Ernest Wayne, Wojnarowski, Robert John, Douglas, Leonard Richard
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US10/136,626
• Publication Number:
  US 20020121691A1
• Time in Patent Office: 460 Days
• Field of Search: 257/77, 257/744, 257/773
• US Class Current: 257/77
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1301 Thyristor

Abstract

A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

Claims

1. A high-temperature circuit apparatus comprising:

(a) high-temperature silicon carbide (SiC) devices situated on a substrate and comprising working and non-working devices; and

(b) interconnection paths interconnecting the working devices and excluding the non-working devices in accordance with an operational characteristics map the interconnection paths comprising

(1) a current-balancing resistive metal and via connections between the current-balancing resistive metal and bonding pads of the working devices, and

(2) a high-temperature shunt metal over the current-balancing resistive metal, the high-temperature shunt metal having notches therein for altering electrical resistances of the interconnection paths in accordance with the operational characteristics map.

2. The apparatus of claim 1, wherein the interconnection paths are adapted to balance current flows through each of the working devices in accordance with the operational characteristics map.

3. The apparatus of claim 1, wherein the interconnection paths are adapted to balance current flows through each of the working devices.

4. The apparatus of claim 1, wherein the interconnection paths are adapted to generate a substantially uniform heat distribution over the devices in accordance with the operational characteristics map.

5. The apparatus of claim 1, further comprising resistor temperature devices positioned in selected ones of the notches in accordance with the operational characteristics map.

6. The apparatus of claim 1, further including fuse links in the current-balancing resistive metal underlying at least some of the notches.

7. The apparatus of claim 1, wherein the current-balancing resistive metal is patterned to comprise variable widths in accordance with the operational characteristics map.

8. The apparatus of claim 1, wherein the via connections between the current-balancing resistive metal and the bonding pads comprise die-pad-to-preform connection structures.

9. The apparatus of claim 1, wherein the via connections comprise braze plugs.

10. The apparatus of claim 1, wherein the via connections comprise weld straps.

11. The apparatus of claim 1, wherein the current balancing resistive metal comprises a metal preform layer and having pre-fabricated via holestherein.

12. A high-temperature circuit apparatus comprising:

(a) high-temperature silicon carbide (Sic) segments each comprising a plurality smaller high-temperature silicon carbide devices including working and non-working devices; and

(b) interconnection paths interconnecting the working devices and excluding the non-working devices in accordance with an operational characteristics map such that each segment operates as an integrated device, the interconnection paths comprising

(1) a current-balancing resistive metal and via connections between the current-balancing resistive metal and bonding pads of the smaller devices, and

(2) a high-temperature shunt metal over the current-balancing resistive metal, the high-temperature shunt metal having notches therein for altering electrical resistances of the interconnection paths in accordance with the operational characteristics map.

13. The apparatus of claim 12, further including fuse links in the current-balancing resistive metal underlying at least some of the notches.