Electrostatic discharge protection circuit device

• US 6,603,177 B2
• Filed: 05/18/2001
• Issued: 08/05/2003
• Est. Priority Date: 05/18/2001
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tang, Tien-Hao, Chen, Shiao-Shien
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Smith, Bradley
• Application Number:
  US09/860,973
• Publication Number:
  US 20020171110A1
• Time in Patent Office: 809 Days
• Field of Search: 257/337, 257/551, 257/156, 257/356, 257/499, 257/506, 257/355
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

A structure of an ESD protection circuit device located under a pad, protecting an internal circuit and a method of manufacturing the same are disclosed. The ESD protection circuit device having a pad window, located under a pad, includes a semiconductor substrate having a P-well and an N well. The P-well and the N-well have an interface. A predetermined area, pad window is selected in the substrate. A first STI structure, a second STI structure and a third STI structure are formed in the substrate within the pad window. N-type doped regions are formed P-well and in the N-well. First p-type doped regions are formed in the P-well and in the N-well and second p-type doped regions are formed in the P-well and in the N-well. A first zener diode is formed in the N-well and a second zener diode is formed in the P-well.

Claims

1. A structure of an electrostatic discharge (ESD) protection circuit, located under a pad which is to be formed later, the structure comprising:

a substrate having a P-well and a N-well, wherein the P-well and the N-well have an interface, wherein a pad window is selected in the substrate which crosses over the interface, wherein the pad window is located under the pad;

a first shallow trench isolation structure, a second shallow trench isolation structure, a third shallow trench isolation structure formed in the substrate within the pad window, wherein the first shallow trench isolation structure is located over the interface, the second shallow trench isolation structure is located in the P-well and the third shallow trench isolation structure is located in the N-well, wherein the second shallow trench isolation structure encloses a first inner region that is separated from a first outer region and the third shallow trench isolation encloses a second inner region that is separated from a second outer region;

a plurality of n-type doped regions formed in the first inner region of the P-well and in the second inner region of the N-well;

a plurality of first p-type doped regions formed in the first outer region of the P-well and in the second outer region of the N-well; and

a plurality of second p-type doped regions formed in the outer regions under the n-type doped regions, wherein one of the second p-type doped regions, which is under the second inner region, has an electrical contact with the n-type doped region in the N-well to form a first zener diode, and another of the second p-type doped regions, which is under the first inner region, has an electrical contact with the n-type doped region in the P-well to form a second zener diode.

2. The structure of claim 1, wherein the P-well comprises boron dopants.

3. The structure of claim 1, wherein the N-well comprises phosphorous dopants.

4. The structure of claim 1, wherein the first p-type doped region in the P-well and the first p-type doped region in the N-well are formed by implanting boron with a concentration higher than the P-well.

5. The structure of claim 1, wherein the second p-type doped region in the P-well and in the N-well are formed by implanting boron with a dosage level slightly lower than the first p-type doped region.

6. The structure of claim 1, wherein the n-type doped region in the P-well and in the N-well are formed by implanting phosphorous with a concentration higher than the N-well.

7. The structure of claim 1, wherein the first p-type doped region of the N-well is electrically connected to the pad, the n-type doped region of the N-well is electrically connected to a system power source, and the first p-type doped region of the P-well is electrically connected to ground.