LDO regulator having an adaptive zero frequency circuit

• US 6,603,292 B1
• Filed: 04/11/2001
• Issued: 08/05/2003
• Est. Priority Date: 04/11/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: O'Kane, Steve, Schouten, Andre
• Primary Examiner(s): Riley; Shawn
• Application Number:
  US09/834,216
• Time in Patent Office: 846 Days
• Field of Search: 323/316,313,273,280,274,277
• US Class Current: 323/277
• CPC Class Codes: G05F 1/573 with overcurrent detector
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A low dropout voltage (LDO) regulator having an adaptive zero frequency circuit is described. The adaptive zero frequency circuit maintains the stability of the LDO regulator and improves the transient response of the LDO regulator under a range of values for the output current, whereas the output current inversely varies with the load resistance coupled to the output of the LDO regulator. The adaptive zero frequency circuit generates a zero having a frequency which varies with the output current. Hence, the frequency of the zero changes to maintain the stability of the LDO regulator despite the variation in the frequency of the low-frequency pole generated by the load resistance and the load capacitance (or output capacitor) coupled to the output of the LDO regulator.

Claims

1. A frequency compensation circuit for a low dropout voltage (LDO) regulator having an amplifying stage and a pass device stage, comprising:

a current sensing circuit coupled to said pass device stage, said current sensing circuit generating a sense current that varies with an output current generated by said pass device stage; and

an adaptive zero frequency (AZF) circuit coupled to said current sensing circuit, coupled to a ground terminal of said LDO regulator, and coupled to an output terminal of said amplifying stage, wherein said AZF circuit provides a zero in a transfer function equation associated with a frequency response of said LDO regulator, and wherein said zero is located at a frequency which varies with said sense current so that to maintain stability in said LDO regulator and to improve transient response of said LDO regulator under a range of values for said output current.

2. A frequency compensation circuit as recited in claim 1 wherein said adaptive zero frequency (AZF) circuit comprises a variable resistance device having a resistance which inversely varies with a bias parameter, a capacitor coupled to said variable resistance device, and a bias circuit coupled to said variable resistance device for generating said bias parameter in response to said sense current, wherein said zero is generated by said variable resistance device in series with said capacitor, and wherein said resistance inversely varies with said sense current.

3. A frequency compensation circuit as recited in claim 2 wherein said capacitor comprises an integrated circuit (IC) capacitor.

4. A frequency compensation circuit as recited in claim 2 wherein said variable resistance device comprises a n-channel MOSFET (NMOS) having a drain, a source, and a gate.

5. A frequency compensation circuit as recited in claim 4 wherein said bias circuit comprises a second n-channel MOSFET (NMOS) having a second drain coupled to said current sensing circuit to receive said sense current, a second source coupled to said ground terminal, and a second gate coupled to said second drain, and wherein said gate is coupled to said second gate.

6. A frequency compensation circuit as recited in claim 4 wherein said capacitor includes a first terminal and a second terminal, wherein said first terminal is coupled to said output terminal of said amplifying stage, wherein said drain is coupled to said second terminal, wherein said gate is coupled to said bias circuit such that said bias circuit biases said NMOS in a linear region, wherein said source is coupled to said ground terminal, and wherein said bias parameter comprises a voltage between said gate and said source.

7. A frequency compensation circuit as recited in claim 2 wherein said variable resistance device comprises a p-channel MOSFET (PMOS) having a PMOS drain, a PMOS source, and a PMOS gate.

8. A frequency compensation circuit as recited in claim 7 wherein said bias circuit comprises:

a n-channel MOSFET (NMOS) having a NMOS drain coupled to said current sensing circuit to receive said sense current, a NMOS source coupled to said ground terminal, and a NMOS gate coupled to said NMOS drain;

a second n-channel MOSFET (NMOS) having a second NMOS drain, a second NMOS source coupled to said ground terminal, and a second NMOS gate coupled to said NMOS gate;

a second p-channel MOSFET (PMOS) having a second PMOS drain coupled to said second NMOS drain, a second PMOS source, and a second PMOS gate coupled to said second PMOS drain, wherein said PMOS gate is coupled to said second PMOS gate; and

a secondary biasing circuit coupled to said second PMOS source.

9. A frequency compensation circuit as recited in claim 7 wherein said capacitor includes a first terminal and a second terminal, wherein said first terminal is coupled to said ground terminal, wherein said PMOS drain is coupled to said second terminal, wherein said PMOS gate is coupled to said bias circuit such that said bias circuit biases said PMOS in a linear region, wherein said PMOS source is coupled to said output terminal of said amplifying stage, and wherein said bias parameter comprises a voltage between said PMOS gate and said PMOS source.

10. A frequency compensation circuit as recited in claim 1 wherein said pass device stage comprises a power p-channel MOSFET which generates said output current.

11. A frequency compensation circuit as recited in claim 1 wherein said pass device stage comprises a power PNP transistor which generates said output current.

12. A frequency compensation circuit as recited in claim 1 wherein said current sensing circuit comprises a p-channel MOSFET.

13. A frequency compensation circuit as recited in claim 1 wherein said LDO regulator includes an output and an output capacitor coupled between said output and said ground terminal, wherein said output capacitor includes an equivalent series resistance (ESR), and wherein said stability of said LDO regulator is minimally dependent on said ESR.

14. A frequency compensation circuit as recited in claim 13 wherein said output capacitor comprises a ceramic capacitor.

15. A low dropout voltage (LDO) regulator comprising:

an error amplifier having an amplifying stage and a pass device stage, said error amplifier generating a regulated voltage at an output of said LDO regulator;

a current sensing circuit coupled to said pass device stage, said current sensing circuit generating a sense current that varies with an output current generated by said pass device stage at said output of said LDO regulator; and

an adaptive zero frequency (AZF) circuit coupled to said current sensing circuit, coupled to a ground terminal of said LDO regulator, and coupled to an output terminal of said amplifying stage, wherein said AZF circuit provides a zero in a transfer function equation associated with a frequency response of said LDO regulator, and wherein said zero is located at a frequency which varies with said sense current so that to maintain stability in said LDO regulator and to improve transient response of said LDO regulator under a range of values for said output current.

16. A low dropout voltage (LDO) regulator as recited in claim 15 wherein said adaptive zero frequency (AZF) circuit comprises a variable resistance device having a resistance which inversely varies with a bias parameter, a capacitor coupled to said variable resistance device, and a bias circuit coupled to said variable resistance device for generating said bias parameter in response to said sense current, wherein said zero is generated by said variable resistance device in series with said capacitor, and wherein said resistance inversely varies with said sense current.

17. A low dropout voltage (LDO) regulator as recited in claim 16 wherein said capacitor comprises an integrated circuit (IC) capacitor.

18. A low dropout voltage (LDO) regulator as recited in claim 16 wherein said variable resistance device comprises a n-channel MOSFET (NMOS) having a drain, a source, and a gate.

19. A low dropout voltage (LDO) regulator as recited in claim 18 wherein said bias circuit comprises a second n-channel MOSFET (NMOS) having a second drain coupled to said current sensing circuit to receive said sense current, a second source coupled to said ground terminal, and a second gate coupled to said second drain, and wherein said gate is coupled to said second gate.

20. A low dropout voltage (LDO) regulator as recited in claim 18 wherein said capacitor includes a first terminal and a second terminal, wherein said first terminal is coupled to said output terminal of said amplifying stage, wherein said drain is coupled to said second terminal, wherein said gate is coupled to said bias circuit such that said bias circuit biases said NMOS in a linear region, wherein said source is coupled to said ground terminal, and wherein said bias parameter comprises a voltage between said gate and said source.

21. A low dropout voltage (LDO) regulator as recited in claim 16 wherein said variable resistance device comprises a p-channel MOSFET (PMOS) having a PMOS drain, a PMOS source, and a PMOS gate.

22. A low dropout voltage (LDO) regulator as recited in claim 21 wherein said bias circuit comprises:

a n-channel MOSFET (NMOS) having a NMOS drain coupled to said current sensing circuit to receive said sense current, a NMOS source coupled to said ground terminal, and a NMOS gate coupled to said NMOS drain;

a second n-channel MOSFET (NMOS) having a second NMOS drain, a second NMOS source coupled to said ground terminal, and a second NMOS gate coupled to said NMOS gate;

a second p-channel MOSFET (PMOS) having a second PMOS drain coupled to said second NMOS drain, a second PMOS source, and a second PMOS gate coupled to said second PMOS drain, wherein said PMOS gate is coupled to said second PMOS gate; and

a secondary biasing circuit coupled to said second PMOS source.

23. A low dropout voltage (LDO) regulator as recited in claim 21 wherein said capacitor includes a first terminal and a second terminal, wherein said first terminal is coupled to said ground terminal, wherein said PMOS drain is coupled to said second terminal, wherein said PMOS gate is coupled to said bias circuit such that said bias circuit biases said PMOS in a linear region, wherein said PMOS source is coupled to said output terminal of said amplifying stage, and wherein said bias parameter comprises a voltage between said PMOS gate and said PMOS source.

24. A low dropout voltage (LDO) regulator as recited in claim 15 wherein said pass device stage comprises a power p-channel MOSFET which generates said output current.

25. A low dropout voltage (LDO) regulator as recited in claim 15 wherein said pass device stage comprises a power PNP transistor which generates said output current.

26. A low dropout voltage (LDO) regulator as recited in claim 15 wherein said current sensing circuit comprises a p-channel MOSFET.

27. A low dropout voltage (LDO) regulator as recited in claim 15 further comprising an output capacitor coupled between said output and said ground terminal, wherein said output capacitor includes an equivalent series resistance (ESR), and wherein said stability of said LDO regulator is minimally dependent on said ESR.

28. A low dropout voltage (LDO) regulator as recited in claim 27 wherein said output capacitor comprises a ceramic capacitor.

29. A method of frequency compensating a low dropout voltage (LDO) regulator having an amplifying stage and a pass device stage, said method comprising the steps of:

a) providing a capacitor and a variable resistance device in series between a ground terminal of said LDO regulator and an output terminal of said amplifying stage, wherein said variable resistance device has a resistance which inversely varies with a bias parameter;

b) sensing an output current generated by said pass device stage;

c) generating a sense current that varies with said output current; and

d) generating said bias parameter for said variable resistance device in response to said sense current, wherein said resistance inversely varies with said sense current.

30. A method as recited in claim 29 wherein said variable resistance device in series with said capacitor provide a zero in a transfer function equation associated with a frequency response of said LDO regulator, and wherein said zero is located at a frequency which varies with said sense current so that to maintain stability in said LDO regulator and to improve transient response of said LDO regulator under a range of values for said output current.

31. A method as recited in claim 29 wherein said variable resistance device comprises a n-channel MOSFET (NMOS), wherein said NMOS is coupled to said ground terminal and is coupled to said capacitor, and wherein said capacitor is coupled to said output terminal.

32. A method as recited in claim 29 wherein said variable resistance device comprises a p-channel MOSFET (PMOS), wherein said PMOS is coupled to said output terminal and is coupled to said capacitor, and wherein said capacitor is coupled to said ground terminal.

33. A method as recited in claim 29 wherein said pass device stage comprises a power p-channel MOSFET which generates said output current.

34. A method as recited in claim 29 wherein said pass device stage comprises a power PNP transistor which generates said output current.

35. A method as recited in claim 29 wherein said LDO regulator further includes an output capacitor coupled between an output of said LDO regulator and said ground terminal, wherein said output capacitor includes an equivalent series resistance (ESR), and wherein stability of said LDO regulator is minimally dependent on said ESR.

36. A method as recited in claim 35 wherein said output capacitor comprises a ceramic capacitor.

37. A method as recited in claim 29 wherein said steps b) and c) are performed by a p-channel MOSFET.