Ramp circuit to reduce spectral regrowth of power amplifiers

• US 6,603,335 B1
• Filed: 06/11/2002
• Issued: 08/05/2003
• Est. Priority Date: 06/11/2002
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: SIGE Semiconductor Incorporated (Skyworks Solutions Incorporated)
• Inventors: Macphail, Phil, An, Wei
• Primary Examiner(s): Ton, My-Trang Nu
• Application Number:
  US10/167,633
• Time in Patent Office: 420 Days
• Field of Search: 327/131, 327/132, 327/133, 327/134, 327/135, 327/136, 327/170, 323/315, 330/253, 330/257, 330/307
• US Class Current: 327/131
• CPC Class Codes: H03K 17/163 Soft switching

Abstract

A circuit for controlling a high frequency power amplifier for amplifying a signal for wireless transmission is disclosed. The circuit provides a control signal to the power amplifier at an output port thereof. The control signal has properties of rise time and fall time, where a delayed transition in this signal is based on charging and discharging of the capacitor using two current mirror circuits in order to provide the delayed transition. An advantage lies in that the time of this delayed transition is dependent primarily upon the current mirrors and substantially other than dependent upon the RC time constant of the circuit.

Claims

1. An integrated circuit for controlling a high frequency power amplifier for amplifying a signal for wireless transmission comprising:

an output port;

an integrated capacitor electrically coupled to the output port and absent a comparator circuit coupled thereto; and

,

an integrated current source-sink coupled with the integrated capacitor for providing current thereto and sinking current therefrom, the integrated current source-sink operable in a first mode to charge the integrated capacitor and operable in a second mode to discharge the integrated capacitor;

wherein, in use, a transition between said first mode and said second mode results in a delayed transition of an output signal at the output port between first and second output signal levels having a transition time of the delayed transition being substantially unrelated to an RC time constant of the integrated circuit.

2. An integrated circuit according to claim 1, wherein the integrated circuit is absent a substantial resistance in series with the integrated capacitor, such that the delay time is substantially dependent on a capacitance of the integrated capacitor and a current of the integrated current source-sink.

3. An integrated circuit according to claim 1, wherein said time constant is dependent on a small integrated resistor in series with the capacitor, said integrated resistor being small in value such that said time constant is substantially dependent on a capacitance of the integrated capacitor and a current of the integrated current source-sink.

4. An integrated circuit according to claim 1, wherein said integrated current source-sink comprises an upper current mirror integrated circuit coupled to the integrated capacitor for charging thereof.

5. An integrated circuit according to claim 4, wherein said integrated current source-sink comprises a lower current mirror integrated circuit coupled to the integrated capacitor for discharging thereof.

6. An integrated circuit according to claim 5, wherein said upper current mirror integrated circuit comprises:

first and second PMOS transistors and said lower current mirror integrated circuit comprises;

first and second NMOS transistors.

7. An integrated circuit according to claim 4, wherein said upper current mirror integrated circuit comprises:

first and second PMOS transistors.

8. An integrated circuit according to claim 1, wherein said integrated current source-sink and said integrated capacitor occupying an area smaller than an area of an RC circuit for supporting a same delay.

9. An integrated circuit according to claim 1, wherein said integrated capacitor comprising a resistance in series therewith other than configured to form a low pass filter within the integrated circuit.

10. An integrated circuit according to claim 1, comprising:

an input port for receiving a control signal for selecting between current source/sink state.

11. An integrated circuit according to claim 10, comprising:

an integrated power amplifier circuit coupled to the output port for receiving the output signal and for varying a power supply voltage provided to said integrated power amplifier circuit in dependence upon the control signal.

12. An integrated circuit according to claim 11, wherein the integrated power amplifier is for use in a BlueTooth™

wireless transmitter.

13. An integrated circuit according to claim 1, wherein the delay time is approximately equal in time for a transition from first to second output signal levels as for a transition from second to first output signal levels.

14. An integrated circuit according to claim 13, wherein the transition time is between 1 and 2 microseconds.

15. A method of modulating a power amplifier output signal level comprising the steps of:

providing a capacitor;

receiving a control signal having one of a first level and a second level;

initiating a charging of said capacitor at a linear rate when said control signal changes from the second level to the first level;

varying the power amplifier output signal level from minimum level to a maximum level during a continuous linear charging of said capacitor, where a time taken for said charging is a first transition time;

initiating a discharge of said capacitor at the linear rate when said control signal changes from the first level to the second level; and

,

varying the power amplifier output signal level from the maximum level to the minimum level during a continuous linear discharging of said capacitor, where a time taken for said charging is a second transition time.

16. A method according to claim 15, comprising the step of:

providing an input signal to said power amplifier;

amplifying said input signal using an approximately maximal gain of said power amplifier when operating at the maximum level.

17. A method according to claim 16, comprising the step of:

providing an input signal to said power amplifier;

attenuating said input signal using an approximately maximal attenuation of said power amplifier when operating at the minimum level.

18. A method according to claim 15, comprising the step of:

providing an input signal to said power amplifier;

attenuating said input signal using an approximately maximal attenuation of said power amplifier when operating at the minimal level.

19. A method according to claim 15, wherein the first transition time and the second transition time are approximately equal.

20. A method according to claim 19, wherein the first transition time and the second transition time are between 1 and 2 microseconds.

21. A method according to claim 15, wherein the amplifier is for use in amplifying a signal for transmission via a wireless communication medium.

22. An integrated circuit for amplifying a signal for wireless transmission comprising:

a first input port for receiving a first input signal for amplification thereof;

an output port;

a control port for receiving a control signal;

an integrated capacitor electrically coupled to the control port for providing a control signal thereto in dependence upon a charge on the integrated capacitor and absent a comparator circuit coupled thereto;

an integrated source current mirror electrically coupled with the capacitor and integrated therewith;

an integrated sink current mirror electrically coupled with the integrated capacitor, the integrated source and sink current mirrors for providing current to the integrated capacitor and sinking current therefrom, the integrated current mirrors operable in a first mode to charge the integrated capacitor and operable in a second mode to discharge the integrated capacitor; and

,

an integrated power amplifier circuit coupled to the first input port for receiving the first input signal and for amplifying the first input signal in dependence upon the control signal, the amplified first input signal forming the output signal and provided at the output port;

wherein, in use, a transition between said the first mode and the second mode results in a delayed transition of the control signal at the control port between first and second control signal levels, with a transition time of the delayed transition being substantially unrelated to an RC time constant of the integrated circuit.