Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator

• US 6,603,339 B2
• Filed: 12/14/2001
• Issued: 08/05/2003
• Est. Priority Date: 12/14/2001
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Atallah, Francois I., Correale, Anthony Jr.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/017,744
• Publication Number:
  US 20030112045A1
• Time in Patent Office: 599 Days
• Field of Search: 327/170, 327/172, 327/175, 327/176, 327/145, 327/149, 327/150, 327/152, 327/158, 327/159, 327/161, 327/261, 327/263, 327/271, 327/274
• US Class Current: 327/175
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

An incoming signal'"'"'s duty cycle is transformed to a known value by a first programmable duty cycle generator, and the output of the first programmable duty cycle generator is applied to a second programmable duty cycle generator which includes multiple stages which provide multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other by voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

Claims

1. A programmable circuit for generating a plurality of phase aligned output clock signals, each having a different desired duty cycle, comprising:

a first duty cycle generator for converting an input clock signal of unknown duty cycle to a known and programmable duty cycle;

a second duty cycle generator connected in series with the output of the first duty cycle generator, including multiple stages providing multiple tap point output signals, each with a known and precise duty cycle value, for phase aligning the multiple tap point output signals with respect to each other.

2. The circuit of claim 1, wherein the leading edges of the multiple tap point output signals are phase aligned with respect to each other.

3. The circuit of claim 1, wherein the lagging edges of the multiple tap point output signals are phase aligned with respect to each other.

4. The circuit of claim 1, wherein one or more of the multiple output signals are delayed by a precise delay needed to phase align each of the multiple output signals.

5. The circuit of claim 4, wherein each precise delay is introduce by one or more voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

6. The circuit of claim 4, wherein the second duty cycle generator comprises:

an operational amplifier for comparing an analog voltage representing the desired duty cycle with an analog feedback voltage Vcont, and generating an output control signal in response thereto;

a voltage controlled duty cycle generator, responsive to the output control signal of the operational amplifier and having an input clock signal, for generating an output clock signal having the desired duty cycle, wherein the voltage controlled duty cycle generator comprises a plurality of stages;

a low pass filter, responsive to the output clock signal, for measuring the duty cycle of the output clock signal and for generating the analog feedback voltage Vcont for the operational amplifier, thereby providing a closed feedback loop operation.

7. The circuit of claim 6, wherein the operational amplifier comprises an operational transconductance amplifier which generates an output current proportional to a difference of its input voltages;

and

a capacitor for receiving the generated output current and for charging or discharging the capacitor to produce a voltage across the capacitor which controls the voltage controlled duty cycle generator.

8. The circuit of claim 6, wherein each precise delay is introduced by one or more voltage controlled delay matching elements which are replicas of the stages of the voltage controlled delay duty cycle generator.

9. The circuit of claim 8, wherein each stage of the second duty cycle generator and the voltage controlled delay duty cycle generator comprises a current starved inverter which includes at least one PFET current source and at least one NFET current source.

10. The circuit of claim 9, wherein the second duty cycle generator includes a Vcontc generator for generating a complement of the analog feedback voltage Vcont.

11. The circuit of claim 10, wherein, in each voltage controlled delay matching elements, for a rising edge alignment, Vcontc is applied to the nfet gate of the current starved inverter while Vcont is applied to the pfet gate of the current starved inverter.

12. The circuit of claim 10, wherein, in each voltage controlled delay matching elements, for a falling edge alignment, Vcontc is applied to the pfet gate of the current starved inverter while Vcont is applied to the pnfet gate of the current starved inverter.

13. The circuit of claim 6, wherein the first duty cycle generator comprises:

an operational amplifier for comparing an analog voltage representing the desired duty cycle with an analog feedback voltage, and generating an output control signal in response thereto;

a voltage controlled duty cycle generator, responsive to the output control signal of the operational amplifier and having an input clock signal, for generating an output clock signal having the desired duty cycle, wherein the voltage controlled duty cycle generator comprises a plurality of stages; and

a low pass filter, responsive to the output clock signal, for measuring the duty cycle of the output clock signal and for generating the analog feedback voltage for the operational amplifier, thereby providing a closed feedback loop operation.

14. The circuit of claim 13, wherein each operational amplifier comprises an operational transconductance amplifier for generating an output current proportional to a difference of its input voltages;

and

a capacitor for receiving the generated output current and for charging or discharges the capacitor to produce a voltage across the capacitor which controls the voltage controlled duty cycle generator.

15. The circuit of claim 13, wherein the output of a digital to analog converter is applied to a noninverting input of the operational amplifier, and the output of the low pass filter is applied to an inverting input of the operational amplifier, such that the voltage controlled duty cycle generator inverts the clock signal to produce the output clock signal.

16. The circuit of claim 13, wherein each voltage controlled duty cycle generator comprises a plurality of stages, each of which comprises a current starved inverter, comprised of PFET current sources and NFET current sources followed by a series inverter which presents a capacitive load to the current sources, to provide either additive or subtractive duty cycle corrections, the plurality of current starved inverters being controlled by the output control signal voltage of the operational amplifier which is connected to both the PFET current sources and the NFET current sources, and as the output control voltage increases, the PFET current sources provide a smaller current to charge the capacitive load, and the NFET current sources provide a larger current to discharge the capacitive load, such that the output waveform has a slow rising edge and a fast falling edge, and the difference in edge rates causes the output of the inverter to have a longer falling delay than a rising delay to produce a duty cycle that is controlled by the output control signal voltage of the operational amplifier.

17. The circuit of claim 16, wherein each of the plurality of stages is followed by an inverter.

18. The circuit of claim 13, wherein each low pass filter comprises an RC low pass filter.

19. The circuit of claim 1, including a buffer at each tap point output to isolate the output load from the internal circuit of the second duty cycle generator.

20. The circuit of claim 19, wherein the duty cycle offset due to each buffer is compensated for by the insertion of a like buffer in the feedback loop.