High data rate vector demodulator

• US 6,603,368 B1
• Filed: 03/06/2002
• Issued: 08/05/2003
• Est. Priority Date: 03/06/2002
• Status: Active Grant

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Inventors: Sylvester, Randal R., Leahy, Ronald S., Simkins, James M.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US10/092,865
• Time in Patent Office: 517 Days
• Field of Search: 332/100-105, 329/300-306, 329/345, 329/346, 375/340-343
• US Class Current: 332/100
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033

Abstract

A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter. As a result, the maximum symbol rate—and hence the maximum data rate—is raised up to N times the device maximum clock rate for waveforms such as Biphase Shift Keying, where N represents the number of data elements in the vectors, and 2N for waveforms such as Quadrature Phase Shift Keyed. The data rate is increased by a factor of N for one sample per symbol, and by a factor of N/2 for 2 samples per symbol, etc.

Claims

1. A method of demodulating data signal waveforms via a demodulator residing in a device, said method comprising the steps of:

a) serially receiving an input waveform with a symbol rate M;

b) converting said input waveform into input vectors, each vector having a predetermined number of samples;

c) for each device clock period, where the maximum device clock speed is R, processing an input vector by making soft decisions to demodulate said input vectors into output vectors containing data estimates as elements; and

d) outputting the elements of said output vectors as demodulated data;

wherein M is greater than R.

2. The method in claim 1, wherein said data signal waveforms are modulated using Phase Shift Keying.

3. The method in claim 1, wherein said data signal waveforms are modulated using Quadrature Amplitude Modulation.

4. The method in claim 1, wherein said data signal waveforms contain one sample per symbol period.

5. The method in claim 1, wherein said data signal waveforms contain at least two samples per symbol period.

6. The method in claim 1, wherein step c) also comprises the step of preprocessing said input vectors to provide matched filtering and remove DC bias levels in said input vectors.

7. The method in claim 1, wherein step c) also comprises the step of, via a digital phase shifter, removing any residual carrier signal in said input vectors and phase errors.

8. The method in claim 7, wherein step c) also comprises the step of, via a symbol demodulator having a phase error detector and a phase loop filter, outputting to said digital phase shifter, a phase rotator command signal, wherein said digital phase shifter is responsive thereto.

9. The method in claim 8, wherein step c) also comprises the step of, via an equalizer, minimizing the effects of Inter Symbol Interference in the output of said digital phase shifter.

10. The method in claim 9, further comprising the step of controlling said equalizer via said symbol demodulator.

11. A demodulator residing in a device, said demodulator adapted to demodulate data signal waveforms, and said demodulator comprising:

an input adapted to serially receive an input waveform with a symbol rate M;

a serial-to-parallel multiplexer adapted to convert said input waveform into input vectors, each vector having a predetermined number of samples;

a vector demodulator adapted to, for each device clock period, where the maximum device clock speed is R, process each input vector to generate an output vector containing soft-decision data estimates as elements; and

a parallel-to-serial multiplexer adapted to output the elements of said output vectors as demodulated data;

wherein M is greater than R.

12. The demodulator in claim 11, wherein said data signal waveforms are modulated using Phase Shift Keying.

13. The demodulator in claim 11, wherein said data signal waveforms are modulated using Quadrature Amplitude Modulation.

14. The demodulator in claim 11, wherein said data signal waveforms contain one sample per symbol period.

15. The demodulator in claim 11, wherein said data signal waveforms contain at least two samples per symbol period.

16. The demodulator in claim 11, wherein said vector demodulator also comprises a preprocessor adapted to preprocess said input vectors to provide matched filtering and remove DC bias levels in said input vectors.

17. The demodulator in claim 11, wherein said vector demodulator also comprises a digital phase shifter adapted to remove any residual carrier signal in said input vectors and phase errors.

18. The demodulator in claim 17, wherein said vector demodulator also comprises a symbol demodulator having a phase error detector and a phase loop filter, said symbol demodulator adapted to output to said digital phase shifter, a phase rotator command signal, wherein said digital phase shifter is responsive thereto.

19. The demodulator in claim 18, wherein said vector demodulator also comprises an equalizer adapted to minimize the effects of Inter Symbol Interference in the output of said digital phase shifter.

20. The demodulator in claim 19, wherein said symbol demodulator is further adapted to control said equalizer.