Using a single control line to provide select and reset signals to image sensors in two rows of a digital imaging device

• US 6,603,513 B1
• Filed: 02/16/1999
• Issued: 08/05/2003
• Est. Priority Date: 02/16/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Berezin, Vladimir
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/250,623
• Time in Patent Office: 1,631 Days
• Field of Search: H04/N.5335, 348/294, 348/295, 348/296, 348/297, 348/302, 348/303, 348/308, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A digital imaging system, such as an active pixel sensor (APS) system, includes an array of sensors arranged into lines that form rows and columns. Each sensor in the array includes a photosensor that collects electric charge when exposed to light. Each sensor also includes a select circuit that generates an output signal indicating the amount of charge collected by the photosensor during a given time, and a reset circuit that clears collected charge from the sensor at a selected time. The APS system also includes a line decoder circuit that produces select and reset signals and delivers the signals to the select circuits over control lines. Each control line connects to two adjacent lines, e.g., rows or columns, of the array, delivering a select signal to the image sensors in one of the two lines and delivering a reset signal to the image sensors in the other line.

Claims

1. A digital imaging device comprising:

a plurality of image sensors arranged into an array of lines including rows and columns;

at least one output line connected to the image sensors; and

a control line connected electrically to at least two different image sensors in two different lines and configured to deliver a select signal to at least one image sensor in a first one of the lines and to deliver a reset signal to at least one image sensor in a second one of the lines, where the select signal causes the image sensor in the first line to place an output signal on the output line, and where the reset signal clears information from the image sensor in the second line.

2. The digital image device of claim 1, wherein the lines to which the control line connects are rows.

3. The digital image device of claim 1, wherein the lines to which the control line connects are columns.

4. The digital imaging device of claim 1, wherein the image sensor includes a photosensor.

5. The digital imaging device of claim 4, wherein the image sensor in the first line includes a select switch connected. between the photosensor and the control line and configured to conduct when the select signal is received.

6. The digital imaging device of claim 5, wherein the select switch includes a transistor.

7. The digital imaging device of claim 4, wherein the image sensor in the second line includes a reset switch connected between the photosensor and the control line and configured to conduct when the reset signal is received.

8. The digital imaging device of claim 7, wherein the reset switch includes a transistor.

9. The digital imaging device of claim 1, further comprising a control circuit connected to the control line and configured to produce the reset signal and the select signal.

10. The digital imaging device of claim 9, wherein the control circuit is configured to produce the reset signal before producing the select signal.

11. The digital imaging device of claim 9, wherein the control circuit is configured to produce the reset signal and the select signal separated by a time increment approximately equal to a row clock period of the imaging device.

12. The digital imaging device of claim 4, wherein said photosensor is a photodiode.

13. The digital imaging device of claim 4, wherein said photosensor is a photogate.

14. A digital imaging system comprising:

a plurality of image sensors arranged into an array of lines including rows and columns, each image sensor including;

a photosensor configured to collect electric charge when exposed to light;

a select circuit coupled to the photosensor to generate an output signal indicating an amount of electric charge collected by the photosensor; and

a reset circuit coupled to the photosensor to remove collected charge from the photosensor; and

a line decoder circuit including;

a control circuit configured to produce select signals and reset signals; and

a plurality of control lines, each of which is connected to image sensors in two of the lines, and each of which is configured to deliver one of the select signals to the select circuits of image sensors in one of the two lines and to deliver one of the reset signals to the reset circuits of image sensors in the other of the two lines.

15. The digital imaging system of claim 14, wherein the control circuit is configured to generate the reset signal for each control line before generating the select signal for the control line.

16. The digital imaging system of claim 14, wherein the select circuit in each image sensor includes a source-follower transistor coupled to a switching transistor.

17. The digital imaging system of claim 16, wherein the gates of each of the switching transistors in one of the rows are driven by a select signal delivered by one of the control lines.

18. The digital imaging system of claim 16, wherein the source-follower transistor is configured to convert electric. charge collected by the photosensor into an output voltage.

19. The digital imaging system of claim 14, wherein the reset circuit in each image sensor includes a switching transistor.

20. The digital imaging system of claim 19, wherein the gates of each of the switching transistors in one of the lines are driven by a reset signal delivered by one of the control lines.

21. The digital imaging system of claim 14, wherein the lines to which each control line connects are rows.

22. The digital imaging system of claim 14, wherein the lines to which each control line connects are columns.

23. A method for use in capturing an image with a plurality of image sensors arranged into an array of lines including rows and columns, the method comprising:

delivering a select signal to at least one image sensor in a first one of the lines and a reset signal to at least one image sensor in a second one of the lines over a single control line;

delivering an output signal from the image sensor in the first one of the lines in response to the select signal; and

clearing information from the image sensor in the second one of the lines in response to the reset signal.

24. The method of claim 23, wherein delivering the output signal from the image sensor in the first line includes delivering the select signal to a select switch in the image sensor and causing the select switch to conduct.

25. The method of claim 23, wherein clearing information from the image sensor in the second line includes delivering the reset signal to a reset switch in the image sensor and causing the reset switch to conduct.

26. The method of claim 23, further comprising delivering the reset signal over the control line before delivering the select signal.

27. The method of claim 23, further comprising delivering the reset signal and the select signal separated by a time increment approximately equal to a row clock period of the array of image sensors.

28. The method of claim 23, wherein the lines to which the control line connects are rows.

29. The method of claim 23, wherein the lines to which the control line connects are columns.

30. An integrated circuit comprising:

a first plurality of pixel cells disposed in a first row, said first plurality of pixel cells having a respective first plurality of reset inputs;

a second plurality of pixel cells disposed in a second row, said second plurality of pixel cells having a respective second plurality of select inputs, said second row disposed in spaced relation to said first row; and

a signal line mutually coupled to said first plurality of reset inputs and said second plurality of select inputs.

31. An integrated circuit as defined in claim 30 wherein said signal line is disposed in spaced relation between said first and second rows.

32. An integrated circuit as defined in claim 30 wherein said signal line is adapted to couple a signal transition to said first plurality of reset inputs and said second plurality of select inputs substantially simultaneously.

33. An integrated circuit as defined in claim 32 further comprising a row driver coupled to said signal line and adapted to generate said signal transition on said signal line.

34. An integrated circuit device as defined in claim 30 wherein said pixel cells are active pixel sensor cells.

35. An integrated circuit device as defined in claim 30 wherein said first and second pluralities of pixel cells comprise first and second pluralities of charge coupled device cells.

36. A method of operating an optical sensor having first, second and third pixel circuits comprising:

receiving a first signal at a first reset input of said first pixel circuit and at a second select input of said second pixel circuit substantially simultaneously during a first time interval, said first signal being received over a first common signal line;

receiving a second signal at a third reset input of said second pixel circuit and at a fourth select input of said third pixel circuit substantially simultaneously during a second time interval, said second signal being received over a second common signal line;

resetting said first pixel circuit and selecting said second pixel circuit substantially simultaneously during said first time interval; and

resetting said second pixel circuit and selecting said third pixel circuit substantially simultaneously during said second time interval.

37. A method of operating an imager array comprising:

receiving a signal at a first plurality of inputs of a respective first plurality of sensor cells;

receiving said signal at a second plurality of inputs of a respective second plurality of sensor cells, said signal received at said first and second pluralities of inputs substantially simultaneously over a common signal line;

resetting said first plurality of sensor cells responsive to said signal; and

selecting said second plurality of sensor cells responsive to said signal.

38. A method of operating an imager array as defined in claim 37 where each said sensor cell is a charge coupled device cell.

39. A method of operating an imager array as defined in claim 37 where each said sensor cell is a active pixel sensor cell.

40. A method of operating an active pixel sensor array as defined in claim 37 wherein said signal comprises a signal transition from a first logic state to a second logic state.

41. A method of forming an imager array comprising:

forming a first row of cells including a first plurality of sensors over a semiconductor substrate;

forming a second row of cells including a second plurality of sensors over said semiconductor substrate, said first and second rows of cells disposed in spaced relation to one another;

forming a signal line over said semiconductor substrate and disposed in spaced relation to said first and second rows of cells;

coupling said signal line to a first plurality of reset inputs and a second plurality of select inputs of said first and second rows of cells respectively;

forming a diver circuit over said semiconductor substrate; and

coupling said signal line to an output of said driver circuit.

42. A method of forming an imager array as defined in claim 41 further comprising:

forming a row decoder circuit over said semiconductor substrate; and

coupling an output of said row decoder circuit to an input of said driver circuit.

43. A method of forming an imager array as defined in claim 41 wherein each said sensor cell is a charge coupled device sensor cell.

44. A method of forming an imager array as defined in claim 41 where each said sensor cell is an active pixel sensor cell.

45. An imager array comprising:

means for generating a control signal; and

single conductor means for conveying said control signal to a first plurality of image sensor cells and a second plurality of image sensor cells, said signal adapted to resetting said first plurality of image sensor cells and to selecting said second plurality of image sensor cells, said resetting and selecting occurring substantially simultaneously.

46. A method of forming an imager array as defined in claim 45 wherein each said image sensor cell is a charge coupled device sensor cell.

47. A method of forming an imager array as defined in claim 45 wherein each said image sensor cell is an active pixel sensor sensor cell.

48. An optical sensor device comprising:

first and second optical sensing circuits having respective select and reset inputs;

a signal line mutually coupled to said select input of said first optical sensing circuit and said reset input of said second optical sensing circuit;

a logic circuit having an output coupled to said signal line, a first logic input adapted to receive a select signal for said first optical sensing circuit, a second logic input adapted to receive a row-select signal for said first optical sensing circuit, and a third logic input adapted to receive a reset signal for said second optical sensing circuit, said logic circuit adapted to produce an output signal on said signal line in response to either a reset signal received at said third logic input or a select signal and a row select signal received concurrently at said first and second logic inputs respectively.

49. An optical sensor device as defined in claim 48 wherein said logic circuit comprises:

an AND gate having a first gate-input coupled to said first logic input and a second gate-input coupled to said second logic input; and

an OR gate having a third gate-input coupled to an output of said AND gate and a fourth gate-input coupled to said third logic input.

50. An optical sensor device as defined in claim 49 wherein said first and second optical sensing circuits are active pixel sensor cells.

51. An optical sensor device as defined in claim 49 wherein said first and second optical sensing circuits are charge coupled devices.