Electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic

• US 6,603,667 B2
• Filed: 05/29/2001
• Issued: 08/05/2003
• Est. Priority Date: 05/30/2000
• Status: Expired due to Fees

• Current Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Ueda, Kazuhiko, Inoue, Akihiko, Sakuma, Hiroshi, Yoshisato, Akiyuki
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US09/870,416
• Publication Number:
  US 20020011352A1
• Time in Patent Office: 798 Days
• Field of Search: 361/734, 361/738, 361/765, 361/766, 361/777, 361/780, 361/782, 361/783, 361/792, 361/794, 257/703, 257/782, 257/783, 257/784, 438/118, 438/119, 333/185, 333/247, 330/66, 330/67
• US Class Current: 361/782
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/092 : Dispersed materials, e.g. conductive pastes or inks
• CPC Class Codes: H05K 2201/0317 : Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 3/246 : Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

The invention provides an electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic. Capacitors and a wiring pattern are formed on an alumina substrate by means of thin film forming technique, and a part of the wiring pattern is served as the connection land for mounting a bare chip of a transistor. Among the capacitors, the top electrode of the capacitor is served also as a part of the connection land, and the bottom side collector electrode of the bare chip is connected to the connection land by use of conductive adhesive. Top electrodes of the residual capacitors are served as the bonding pad, and the base electrode and the emitter electrode on the top side of the bare chip are connected to the top electrodes of the respective capacitors by a wire.

Claims

1. An electronic circuit unit comprising:

an alumina substrate;

a thin film conducting pattern formed on the alumina substrate;

thin film circuit elements including capacitors, resistors, and inductance elements formed on the alumina substrate and connected to the conducting pattern; and

a semiconductor bare chip wire bonded to the conducting pattern,

wherein an area of a connection land on which the semiconductor bare chip is mounted is smaller than a bottom surface area of the semiconductor bare chip.

2. The electronic circuit unit according to claim 1, wherein at least two sides of the semiconductor bare chip are located apart from a contour of the connection land.

3. The electronic circuit unit according to claim 1, wherein an opening is formed in the connection land.

4. The electronic circuit unit according to claim 2, wherein an opening is formed in the connection land.

5. An electronic circuit unit comprising:

a first capacitor formed by laminating a first bottom electrode and a first top electrode with interposition of a first dielectric material on a substrate, and

a semiconductor bare chip mounted on the first capacitor,

wherein the first top electrode serves as a part of a connection land connected to a bottom side electrode of the semiconductor bare chip.

6. The electronic circuit unit according to claim 5, wherein a second capacitor is formed by laminating a second bottom electrode and a second top electrode with interposition of second dielectric material on the substrate, wherein the second top electrode of the second capacitor is wire bonded to a top side electrode of the semiconductor bare chip.