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Decoding scheme for a stacked bank architecture

  • US 6,603,683 B2
  • Filed: 06/25/2001
  • Issued: 08/05/2003
  • Est. Priority Date: 06/25/2001
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device comprising:

  • a plurality of memory bank groups, each memory bank group of said plurality of memory bank groups comprising a plurality of memory banks arranged in a stacked-bank architecture;

    an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks for read/write operations;

    a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks;

    wherein said address bus comprises a global address bus for transferring said read/write bank addresses and read/write addresses for said read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read/write bank addresses and read/write addresses to said decoding units, and wherein said read and write operations may be simultaneously performed in at least two respective memory banks of said each memory bank group.

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