Decoding scheme for a stacked bank architecture

• US 6,603,683 B2
• Filed: 06/25/2001
• Issued: 08/05/2003
• Est. Priority Date: 06/25/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis, Wang, Li-Kong
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US09/888,774
• Publication Number:
  US 20020196669A1
• Time in Patent Office: 771 Days
• Field of Search: 365/189.07, 365/230.03, 365/230.06
• US Class Current: 365/189.04
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A decoding scheme for simultaneously executing multiple operations for a stacked-bank type semiconductor memory device is disclosed. A decoding unit is provided to a memory bank group comprising a plurality of memory banks. When read and write bank addresses match with two different memory banks within the same memory bank group, the decoding unit receives the read and write addresses and generates two different row selection signals for the read and write operations in two different banks. Based on the row selection signals, the row decoder unit in the two matching banks simultaneously activates a target row designated by the read/write addresses.

Claims

1. A semiconductor memory device comprising:

a plurality of memory bank groups, each memory bank group of said plurality of memory bank groups comprising a plurality of memory banks arranged in a stacked-bank architecture;

an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks for read/write operations;

a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks;

wherein said address bus comprises a global address bus for transferring said read/write bank addresses and read/write addresses for said read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read/write bank addresses and read/write addresses to said decoding units, and

wherein said read and write operations may be simultaneously performed in at least two respective memory banks of said each memory bank group.

2. The semiconductor memory device of claim 1, wherein each decoding unit simultaneously transfers said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks.

3. The semiconductor memory device of claim 2, said global address bus comprising:

a global read bank address bus transferring said read bank address for said read operation;

a global write bank address bus transferring said write bank address for said write operation;

a global read address bus transferring a row address of said memory bank matching said read bank address for said read operation; and

a global write address bus transferring a row address of said memory bank matching said write bank address for said write operation.

4. The semiconductor memory device of claim 3, each local address bus comprising:

a local read bank address bus coupled between said global read bank address bus and said corresponding decoding unit, and transferring said read bank address;

a local write bank address bus coupled between said global write bank address and said corresponding decoding unit, and transferring said write bank address;

a local read address bus coupled between said global read address bus and said corresponding decoding unit, and transferring said row address for said read operation; and

a local write address bus coupled between said global write address bus and said corresponding decoding unit, and transferring said row address for said write operation.

5. The semiconductor memory device of claim 4, each of said plurality of decoding units comprising a plurality of register units provided corresponding to said plurality of memory banks of each memory bank group, each register unit generating a row selection signal for either said read operation or said write operation if one of said read/write bank addresses matches said corresponding bank.

6. The semiconductor memory device of claim 5, wherein each register unit comprises a plurality of multiplexing units, each multiplexing unit receiving said read/write bank addresses and said read/write addresses and generating a row selection bit signal, wherein said row selection signal comprises a combination of said row selection bit signals from said plurality of multiplexing units of the same register unit.

7. The semiconductor memory device of claim 6, wherein said row selection signal is provided to a row decoder block of said corresponding memory bank to selectively activate a row of said corresponding memory bank.

8. The semiconductor memory device of claim 7, wherein said row decoder block comprising:

a plurality of row decoders provided corresponding to a plurality of word lines in said corresponding memory bank, each row decoder receiving said row selection signal from said register unit and generating a row activation signal if said row selection signal matches said corresponding row; and

a plurality of word line drivers provided corresponding to said plurality of row decoders, each word line driver activating said corresponding word line based on said row activation signal from said corresponding row decoder.

9. The semiconductor memory device of claim 8, each multiplexing unit comprising:

a latch unit generating said row selection bit signal;

a precharge means for preconditioning the latch unit;

a first decoding means for decoding said read bank address and read address; and

a second decoding path for decoding said write bank address and write bank addresses.

10. The semiconductor memory device of claim 9, wherein said latch unit comprising:

a first inverter having input/output terminals;

a second inverter having input/output terminals;

a first interconnection line interconnecting the output terminal of said first inverter and the input terminal of said second inverter;

a second interconnection line interconnecting the output terminal of said second inverter to the input terminal of said firs t inverter; and

an output node formed on said first interconnection line and generating said row selection bit signal.

11. The semiconductor memory device of claim 10, wherein said precharge means comprising a first voltage source connected to a first node formed on said second interconnection line via a first switching means, wherein said first switching means having a control electrode connected to a precharge signal line.

12. The semiconductor memory device of claim 11, wherein said first decoding means comprising:

a second switch coupled between a second node formed between said first node and said input terminal of said first inverter and a third node, and having a control electrode connected to said local read bank address bus;

a third switch coupled between said third node and a second voltage source, and having a control electrode connected to said local read address bus.

13. The semiconductor memory device of claim 12, wherein said second decoding means comprising:

a fourth switch coupled between a fourth node formed between said first node and said output terminal of said second inverter and a fifth node, and having a control electrode connected said local write bank address bus; and

a fifth switch coupled between said fifth node and said second power source, and having a control electrode connected to said local write address bus.

14. The semiconductor memory device of claim 2, wherein said read bank address and said read address are utilized to execute a refresh operation so that either said read/write operations or said refresh/write operations are simultaneously executed within each memory bank group.

15. A semiconductor memory device comprising:

a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;

an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations; and

a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks;

wherein said address bus comprises a global address bus for transferring said read/write bank addresses and read/write addresses for said read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read/write bank addresses and read/write addresses to said decoding units, and

whereby each memory bank group simultaneously executes at least two of said read, write and refresh operations at least two memory banks thereof.

16. The semiconductor memory device of claim 15, wherein each memory bank group simultaneously executes either said read/write operations or said refresh/write operations at least two memory banks thereof.

17. The semiconductor memory device of claim 16, further comprising a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit simultaneously transferring said read/write addresses to said at least two memory banks if said read/write bank addresses matches said at least two memory banks for said read/write/refresh operations.

18. The semiconductor memory device of claim 17, each of said plurality of decoding units comprising a plurality of register units provided corresponding to said plurality of memory banks of each memory bank group, each register unit generating a row selection signal for either said read operation or said refresh operation if said read bank address matches said corresponding bank and generating a row selection signal for said write operation if said write bank address matches said corresponding bank.

19. The semiconductor memory device of claim 17, each register unit comprising a plurality of multiplexing units, each multiplexing unit receiving said read address and generating a row selection bit signal for said read operation or said refresh operation if said read bank address matches said corresponding bank, and receiving said write address and generate a row selection bit signal for said write operation if said write bank address matches said corresponding bank.

20. An integrated circuit including a memory, said memory including:

at least one memory bank group comprising a plurality of memory banks including at least a first memory bank and a second memory bank arranged in a stacked-bank architecture;

an address bus coupled to said first memory bank and to said second memory bank to provide a write address and a read address to any combination of said first and said second memory banks, and to simultaneously transfer a write address to said first memory bank and a read address to said second memory bank, said read address being selected independently from said write address; and

a plurality of decoding units provided corresponding to a plurality of said at least one memory bank group, each decoding unit transferring said read and write addresses to at least two memory banks of said plurality of memory banks if read and write bank addresses match said at least two memory banks;

wherein said address bus comprises a global address bus for transferring said read and write bank addresses and said read and write addresses for read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read and write bank addresses and said read and write addresses to said decoding units;

whereby, a write operation in said first memory bank may be performed simultaneously with an independent read operation in said second memory bank.

21. The integrated circuit of claim 20 wherein said memory bank group comprises a number n of memory banks, and said address bus includes a number m read paths and said number m write paths, 2m being less than or equal to n, such that said address bus is adapted to simultaneously transfer, one of m independently selected read addresses to each of m said memory banks and one of m independently selected write addresses to each of m other said memory banks, whereby m read operations and m write operations may be performed simultaneously in each of said 2m memory banks.

22. The integrated circuit of claim 21 wherein at least one of said read addresses and said write addresses are adapted to access and refresh stored data in memory locations of said memory bank group, whereby 2m operations being any of read, write or refresh may be performed simultaneously in each of said 2m memory banks.

23. A semiconductor memory device comprising:

a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;

an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations; and

a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit simultaneously transferring said read/write addresses to said at least two memory banks if said read/write bank addresses matches said at least two memory banks for said read/write/refresh operations, each of said plurality of decoding units comprising a plurality of register units provided corresponding to said plurality of memory banks of each memory bank group, each register unit generating a row selection signal for either said read operation or said refresh operation if said read bank address matches said corresponding bank and generating a row selection signal for said write operation if said write bank address matches said corresponding bank;

wherein each memory bank group simultaneously executes at least one of (i) two of said read, write and refresh operations at least two memory banks thereof and (ii) either said read/write operations or said refresh/write operations at least two memory banks thereof.

24. A semiconductor memory device comprising:

a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;

an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations; and

a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit simultaneously transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks for said read/write/refresh operations, each of said plurality of decoding units comprising a plurality of register units, each register unit comprising a plurality of multiplexing units, each multiplexing unit receiving said read address and generating a row selection bit signal for said read operation or said refresh operation if said read bank address matches said corresponding bank, and receiving said write address and generate a row selection bit signal for said write operation if said write bank address matches said corresponding bank;

wherein each memory bank group simultaneously executes at least one of (i) two of said read, write and refresh operations at least two memory banks thereof and (ii) either said read/write operations or said refresh/write operations at least two memory banks thereof.

25. An integrated circuit including a memory, said memory including:

at least one memory bank group comprising a plurality of memory banks including at least a first memory bank and a second memory bank arranged in a stacked-bank architecture, said memory bank group comprises a number n of memory banks; and

an address bus coupled to said first memory bank and to said second memory bank to provide a write address and a read address to any combination of said first and said second memory banks, and to simultaneously transfer a write address to said first memory bank and a read address to said second memory bank, said read address being selected independently from said write address, said address bus includes a number m read paths and said number m write paths, 2m being less than or equal to n, such that said address bus is adapted to simultaneously transfer, one of m independently selected read addresses to each of m said memory banks and one of m independently selected write addresses to each of m other said memory banks, whereby m read operations and m write operations may be performed simultaneously in each of said 2m memory banks, and

whereby a write operation in said first memory bank may be performed simultaneously with an independent read operation in said second memory bank.