Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages

• US 6,603,696 B2
• Filed: 07/31/2002
• Issued: 08/05/2003
• Est. Priority Date: 10/09/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Janzen, Leel S.
• Primary Examiner(s): Le, Thong
• Application Number:
  US10/209,988
• Publication Number:
  US 20030067826A1
• Time in Patent Office: 370 Days
• Field of Search: 365/222, 365/233, 365/226, 365/227, 365/229, 365/189.09, 365/239
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Claims

1. A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode to adjust the value of the bias voltage as a function of a magnitude of the supply voltage;

a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage; and

a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

2. The refresh controller of claim 1 wherein the variable bias voltage generator is operable in the normal mode responsive to the supply voltage being greater than a minimum value, and is operable in the low-power mode responsive to the supply voltage being less than or equal to the minimum value.

3. The refresh controller of claim 1 wherein the bias voltage generator operates in the low-power mode to adjust the bias voltage as a linear function of the supply voltage.

4. The refresh controller of claim 1 wherein the self-refresh oscillator increases the frequency of the refresh clock signal as the bias voltage decreases and decreases the frequency of the refresh clock signal as the bias voltage increases.

5. The refresh controller of claim 1 wherein the refresh control circuit comprises a self-refresh row and bank address counter operable to generate row and bank addresses responsive to the refresh clock signal, the rate at which the row and bank addresses are generated being a function of the frequency of the refresh clock signal and the refresh rate being a function of the rate at which the row and bank addresses are generated.

6. A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode to output the supply voltage as the bias voltage;

a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage; and

a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

7. The refresh controller of claim 6 wherein the voltage bias generator operates in the normal mode responsive to the supply voltage being greater than a minimum value, and operates in the low-power mode responsive to the supply voltage being less than or equal to the minimum value.

8. The refresh controller of claim 6 wherein the self-refresh oscillator increases the frequency of the refresh clock signal as the bias voltage increases and decreases the frequency of the refresh clock signal as the bias voltage decreases.

9. The refresh controller of claim 6 wherein the refresh control circuit comprises a self-refresh row and bank address counter operable to generate row and bank addresses responsive to the refresh clock signal, the rate at which the row and bank addresses are generated being a function of the frequency of the refresh clock signal and the refresh rate being a function of the rate at which the row and bank addresses are generated.

10. A refresh controller for controlling a refresh rate of dynamic data in an integrated circuit, the refresh controller comprising:

a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode responsive to a bias voltage adjustment command that is generated external to the integrated circuit, the variable bias voltage generator operable in response to the command to adjust the value of the bias voltage as a function of a magnitude of the supply voltage;

a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage; and

a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

11. The refresh controller of claim 10 wherein bias voltage adjustment command comprises a load mode register command.

12. The refresh controller of claim 10 wherein the variable bias voltage generator is operable in the normal mode responsive to the supply voltage being greater than a minimum value, and is operable in the-low-power mode responsive to the supply voltage being less than or equal to the minimum value.

13. The refresh controller of claim 10 wherein the bias voltage generator operates in the low-power mode to adjust the bias voltage as a linear function of the supply voltage.

14. The refresh controller of claim 10 wherein the self-refresh oscillator increases the frequency of the refresh clock signal as the bias voltage decreases and decreases the frequency of the refresh clock signal as the bias voltage increases.

15. The refresh controller of claim 10 wherein the refresh control circuit comprises a self-refresh row and bank address counter operable to generate row and bank addresses responsive to the refresh clock signal, the rate at which the row and bank addresses are generated being a function of the frequency of the refresh clock signal and the refresh rate being a function of the rate at which the row and bank addresses are generated.

16. A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

a variable bias voltage generator adapted to receive a supply voltage, the variable bias voltage generator operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a first low-power mode to adjust the value of the bias voltage as a function of a magnitude of the supply voltage and operable in a second low-power mode to output the supply voltage as the bias voltage;

a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage; and

a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

17. The refresh controller of claim 16 wherein the variable bias voltage generator is operable in the normal mode responsive to the supply voltage being greater than a first minimum value, and is operable in the first low-power mode responsive to the supply voltage being less than or equal to the first minimum value and greater than a second minimum value, and is operable in the second low-power mode responsive to the supply voltage being less than or equal to the second minimum value.

18. The refresh controller of claim 17 wherein the bias voltage generator operates in the first low-power mode to adjust the bias voltage as a linear function of the supply voltage.

19. The refresh controller of claim 17 wherein the self-refresh oscillator increases the frequency of the refresh clock signal as the bias voltage increases and decreases the frequency of the refresh clock signal as the bias voltage decreases.

20. The refresh controller of claim 17 wherein the refresh control circuit comprises a self-refresh row and bank address counter operable to generate row and bank addresses responsive to the refresh clock signal, the rate at which the row and bank addresses are generated being a function of the frequency of the refresh clock signal and the refresh rate being a function of the rate at which the row and bank addresses are generated.