Multiplier power saving design

• US 6,604,120 B1
• Filed: 09/04/1997
• Issued: 08/05/2003
• Est. Priority Date: 09/04/1997
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: De Angel, Edwin
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/923,133
• Time in Patent Office: 2,161 Days
• Field of Search: 364/760.04, 364/760.03, 364/760.02, 364/707, 708/631, 708/630, 708/629, 708/628
• US Class Current: 708/631
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: G06F 7/53 in parallel-parallel fashion, i.e. both operands being entered in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/5332 by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm

Abstract

A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. The addition of the rows of the scaled multiplicand input data is performed with adders with two data inputs (plus carryin). These adders are cascaded such that normally invalid data ripples through the adder before the final result is achieved. By controlling the time power is applied to the adders most of the intermediate states are eliminated.

Claims

1. A method for multiplying a multiplicand by a multiplier comprising the steps of:

a) parsing the multiplier into a first plurality of groups of preselected bits of the multiplier and providing a corresponding first plurality of scale factors;

b) scaling the multiplicand by each of said scale factors to provide a first plurality of scaled multiplicands;

c) adding said first plurality of scaled multiplicands together in an adder, said adder comprising a second plurality of adder circuits wherein each of said second plurality of adder circuits has a third plurality of inputs, said third plurality being greater than the number of data bits of any of said first plurality of scaled multiplicands, and wherein said second plurality of adder circuits comprises a fourth plurality of adder circuits and a fifth plurality of adder circuits, said adding step comprising the steps of;

i) applying power to said fourth plurality of adder circuits at the same time and,

ii) applying power to each of said fifth plurality of adder circuits at a fifth plurality of different times such that the number of intermediate states in said second plurality of adder circuits is less than if all of said second plurality of adder circuits were powered at the same time.

2. The method set forth in claim 1 further including the step of applying power to one of said fifth plurality of adder circuits at the same time that power is applied to said fourth plurality of adder circuits.

3. The method set forth in claim 1 further including the step of providing a timer which controls said sequential powering of said fifth plurality of adder circuits in response to a single input signal.

4. A method for multiplying a multiplicand by a multiplier comprising the steps of:

a) parsing the multiplicand into a first plurality of groups of preselected bits of the multiplicand and providing a corresponding first plurality of scale factors;

b) scaling the multiplier by each of said scale factors to provide a first plurality of scaled multipliers;

c) adding said first plurality of scaled multipliers together in a second plurality of adders and controlling the time that power is applied to said second plurality of adders such that at least two adders are powered prior to the start of a multiplication operation, and after said start of said multiplication operation, sequentially powering each of a third plurality of adders such that the number of intermediate states in said third plurality of adders is less than if all of said second plurality of adders were powered at the same time.

5. The method set forth in claim 4 further including the step of powering at least three of said first plurality of adders prior to said start of said multiplication operation.

6. The method set forth in claim 4 further including the step of providing a timer which controls said sequential powering of said third plurality of adders in response to a single input signal.

7. A multiplier for multiplying multiplicand data by signed multiplier data to provide quotient data, said multiplier comprising:

a) an encoder for grouping said multiplier data and for assigning coefficients to each of said groups;

b) a plurality of data selectors coupled to said multiplicand data and to one of said assigned coefficients and providing the product of one of said coefficients times a copy of said multiplicand data; and

c) means for summing coupled to said plurality of registers and providing said quotient data, wherein said means for summing comprises first and second groups of adders, said first group receiving power supply voltage when said a multiplication operation begins, and said second group of adders receiving power supply voltage at a time subsequent to when said first group of adders receives power supply voltage.

8. A method for reducing power in a digital multiplier when said multiplier in successive multiplication operations with identical multiplicand and multiplier data comprising the steps of:

a) encoding said multiplier in CMOS circuitry to provide a first plurality of coefficients;

b) for each of said coefficients multiplying said multiplicand by said respective coefficient to provide a multiplied multiplicand;

c) adding said multiplied multiplicands in a second plurality of adders; and

d) providing power supply voltage to a first set of said adders when said a multiplication operation begins, and providing power supply voltage to a said second set of said adders at a time subsequent to when said first set of adders receives power supply voltage.