Communication of dissimilar data between lock-stepped processors

• US 6,604,177 B1
• Filed: 09/29/2000
• Issued: 08/05/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Klecka, James S., Kondo, Thomas J.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/676,403
• Time in Patent Office: 1,040 Days
• Field of Search: 711/147, 711/150, 711/152, 711/202, 714/11
• US Class Current: 711/150
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/1654 where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1695 which are operating with time diversity

Abstract

A processing system includes a pair of processor coupled in a lockstep arrangement. The pair of processors is coupled to a storage element that is external to the both of them. Each processor executes an instruction stream that is identical to that executed by the other. Dissimilar information can be exchanged between the processors by each writing the information they wish to exchange to a first storage location with identical instructions. Although both processors execute the write with the same address, the information written by one of the processors is redirected to a second storage location. Each processor then reads the first and second storage locations to retrieve information supplied by the other processor. Now each processor has a copy of the other'"'"'s data while staying in lockstep.

Claims

1. In a processing system that includes two processor units each executing identical instructions of instruction streams at substantially the same time, a method of exchanging data between the two processor units, comprising:

writing the data to a first storage location with a first address;

redirecting the first address used by one of the two of processor units to a second address;

reading the content of the first storage location with the first address.

2. The method of claim 1, further comprising:

providing a main memory having a plurality of storage locations accessible to each of the two processor units.

3. The method of claim 2, wherein the first storage location is one of the plurality of storage locations.

4. The method of claim 2, further comprising:

providing a second memory element having the first memory location.

5. The method of claim 4, wherein the second memory element is a, register.

6. The method of claim 1, wherein the two processor units operate in lockstep synchronism to execute the identical instruction streams.

7. A processing system, comprising:

first and second processor units coupled for lockstep operation to execute identical instruction streams;

a storage facility having at least first and second storage locations;

a first instruction in the identical instruction streams to respectively cause each of the first and second processor units to write data to the first storage location;

means for redirecting the data from the second processor unit to the second storage location; and

a second instruction in the identical instruction streams to respectively cause each of the first and second processor units to read the first and second storage locations,

whereby, the first and second processor units exchange data between them.

8. The processing system of claim 7, further comprising:

a main memory accessible to the first and second processor units,

wherein the storage facility forms a part of the main memory.

9. A processing system, comprising:

first and second processor units operating in lockstep to execute substantially identical instruction streams, instruction by instruction;

a main memory shared by the first and second processor units for storing and retrieving data words, each of the data words being protected by error correcting code; and

error correcting circuitry operating to correct errors in data words accessed at the main memory,

wherein the first and second processor units are coupled for exchanging information respecting error counts.

10. A method for exchanging data between two processors engaged in lockstep and compare operations, each of the two processors being associated with a status register, the method comprising:

writing to a first address, by each of the two processors, contents of their associated status register, the first address used by a second of the two processors being redirected to render it different than the first address used by the first of the two processors;

reading, by the two processors, data at the first address;

writing to a second address, by each of the two processors, contents of their associated status register, the second address used by the first of the two processors being redirected to render it different than the second address used by the second of the two processors; and

reading, by the two processors, data at the second address, whereby the two processors are able to exchange dissimilar data without having to diverge from their instruction stream.

11. A method as in claim 10, wherein the contents of each status register includes logged soft memory errors.

12. A method as in claim 10, wherein upon reading the data at the first and second addresses each of the two processors are in possession of addresses, logged by both of them, at which soft memory errors occurred.

13. A method as in claim 12, further comprising:

scrubbing the addresses at which the soft memory errors occurred.

14. A method for exchanging data between two processors engaged in lockstep and compare operations, each of the two processors being associated with a status register, the method comprising:

writing to a first address, by each of the two processors, contents of their associated status register, wherein the content of the status register associated with a second of the two processors is redirected and stored in a second address; and

reading, by the two processors, data at the first and second addresses, whereby the two processors are able to exchange dissimilar data without having to diverge from their instruction stream.

15. A method as in claim 14, wherein the contents of each status register includes logged soft memory errors.

16. A method as in claim 14, wherein upon reading the data at the first and second addresses each of the two processors are in possession of addresses, logged by both of them, at which soft memory errors occurred.

17. A method as in claim 16, further comprising:

scrubbing the addresses at which the soft memory errors occurred.