Reading a FIFO in dual clock domains

• US 6,604,179 B2
• Filed: 03/23/2000
• Issued: 08/05/2003
• Est. Priority Date: 03/23/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Volk, Andrew M., Williams, Michael W.
• Primary Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US09/532,428
• Publication Number:
  US 20020129196A1
• Time in Patent Office: 1,230 Days
• Field of Search: 711/167, 711/154, 711/100, 711/104, 365/220, 365/221, 365/230.05, 365/233, 710/52, 710/54, 710/57, 710/56, 710/29, 710/60-61
• US Class Current: 711/167
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Claims

1. An apparatus, comprising:

a first-in-first-out buffer containing a plurality of addressable storage locations;

a write pointer coupled to the first-in-first-out buffer to point to a first one of the addressable storage locations as an input location;

a first read pointer coupled to the first-in-first-out buffer to point to a second one of the addressable storage locations as a first output location;

a second read pointer coupled to the first-in-first-out buffer to point to a third one of the addressable storage locations as a second output location;

a first clock coupled to the first-in-first-out buffer to clock a destination address for a memory data request into the first-in-first-out buffer at the input location;

a second clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the first output location; and

a third clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the second output location;

wherein the first output location is to provide advance notice that data requested from a memory device is to be available and the second output location is to subsequently provide notice that the data requested from the memory device is available.

2. The apparatus of claim 1, wherein:

the first clock is coupled to the write pointer to increment the write pointer;

the second clock is coupled to the first read pointer to increment the first read pointer; and

the third clock is coupled to the second read pointer to increment the second read pointer.

3. The apparatus of claim 1, wherein each of said write pointer, first read pointer, and second read pointer is a circular pointer.

4. The apparatus of claim 1, wherein each of said first, second and third clocks are different clocks from one another.

5. The apparatus of claim 1, further comprising overrun prevention logic coupled to the write pointer and to the first and second read pointers to prevent the write pointer from incrementing past the first read pointer and to prevent the write pointer from incrementing past the second read pointer.

6. The apparatus of claim 5, wherein the overrun prevention logic includes a status output to indicate a full/empty status of the first-in-first-out buffer.

7. The apparatus of claim 1, further comprising write logic coupled to the write pointer and the first-in-first-out buffer to write the destination address into the storage array at the input location indicated by the write pointer.

8. The apparatus of claim 1, wherein the first-in-first-out buffer has a unified addressing scheme for the write pointer and the first and second read pointers.

9. The apparatus of claim 1, further comprising:

first read logic coupled to the first read pointer and the first-in-first-out buffer to read the destination address from the first-in-first-out buffer at the first output location indicated by the first read pointer; and

second read logic coupled to the second read pointer and the first-in-first-out buffer to read the destination adress from the first-in-first-out buffer at the second output location indicated by the second read pointer.

10. A computer memory controller, comprising:

an interface to a memory bus;

read request logic coupled to the interface to request data from a memory device;

receive logic coupled to the interface and the memory device to receive the data from the memory device and provide the data to a destination address through the interface;

a destination address queue to indicate the destination address for the data received from the memory device, the destination address queue including

a first-in-first-out buffer containing a plurality of addressable storage locations;

a write pointer coupled to the first-in-first-out buffer to point to a first one of the addressable storage locations as an input storage location for the destination address;

a first read pointer coupled to the first-in-first-out buffer to point to a second one of the addressable storage locations as a first output storage location for the destination address;

a second read pointer coupled to the first-in-first-out buffer to point to a third one of the addressable storage locations as a second output storage location for the destination address;

a first clock coupled to the first-in-first-out buffer to clock the destination address into the first-in-first-out buffer at the input storage location;

a second clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the first output storage location; and

a third clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the second output storage location;

wherein the first output storage location is to provide advance notice that the data requested from the memory device is to be available and the second output storage location is to subsequently provide notice that the data requested from the memory device is available.

11. The controller of claim 10 wherein:

the first clock is coupled to the write pointer to increment the write pointer;

the second clock is coupled to the first read pointer to increment the first read pointer; and

the third clock is coupled to the second read pointer to increment the second read pointer.

12. The controller of claim 10, wherein each of said write pointer, first read pointer, and second read pointer is a circular pointer.

13. The controller of claim 10, wherein each of said first, second and third clocks are different clocks from one another.

14. The controller of claim 10, further comprising overrun prevention logic coupled to the write pointer and to the first and second read pointers to prevent the write pointer from incrementing past the first read pointer and to prevent the write pointer from incrementing past the second read pointer.

15. The controller of claim 14, wherein the overrun prevention logic includes a status output to indicate a full/empty status of the first-in-first-out buffer.

16. The controller of claim 10, further comprising write logic coupled to the write pointer and the first-in-first-out buffer to write the destination address into the first-in-first-out buffer at the input storage location indicated by the write pointer.

17. The controller of claim 10, wherein the first-in-first-out buffer has a unified addressing scheme for the write pointer and the first and second read pointers.

18. The controller of claim 10, further comprising:

first read logic coupled to the first read pointer and the first-in-first-out buffer to read the destination address from the first-in-first-out buffer at the first output storage location indicated by the first read pointer; and

second read logic coupled to the second read pointer and the first-in-first-out buffer to read the destination address from the first-in-first-out buffer at the second output storage location indicated by the second read pointer.