Master/slave processor memory inter accessability in an integrated embedded system
First Claim
1. An apparatus comprising:
- one or more first processors each comprising a first random access memory (RAM) section; and
one or more second processors each comprising a read only memory (ROM) section and a second RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.
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Abstract
An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.
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Citations
20 Claims
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1. An apparatus comprising:
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one or more first processors each comprising a first random access memory (RAM) section; and
one or more second processors each comprising a read only memory (ROM) section and a second RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
a plurality of address spaces each specific to a portion of said one or more first processors or a portion of said one or more second processors.
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12. The apparatus according to claim 1, further comprising:
a logic circuit coupled to at least one of said one or more first processors and said one or more second processors.
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13. The apparatus according to claim 1, wherein at least one of said one or more first processors is further configured to notify said one or more second processors after a reset.
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14. The apparatus according to claim 13, wherein said notification determines which code is executed.
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15. An apparatus comprising:
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means for processing code comprising one or more first processors each comprising a Random Access Memory (RAM) section; and
means for processing code comprising one or more second processors each comprising a Read Only Memory (ROM) section and a RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.
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16. A method for implementing interaccessable processors, comprising the steps of:
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(A) processing code comprising one or more first processors each comprising a Random Access Memory (RAM) sections; and
(B) processing code comprising one or more second processors each comprising a Read Only Memory (ROM) section and a RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections. - View Dependent Claims (17, 18, 19, 20)
(C) providing a plurality of address spaces each specific to a first portion of said one or more first processors or a second portion of said one or more second processors.
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Specification