Master/slave processor memory inter accessability in an integrated embedded system

• US 6,604,189 B1
• Filed: 05/22/2000
• Issued: 08/05/2003
• Est. Priority Date: 05/22/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Cohen, Ariel, Zemlyak, Boris
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/576,575
• Time in Patent Office: 1,170 Days
• Field of Search: 712/227, 712/31, 712/43, 712/229, 709/216, 709/209, 709/208, 709/222, 709/211, 711/148, 711/152
• US Class Current: 712/31
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.

Claims

1. An apparatus comprising:

one or more first processors each comprising a first random access memory (RAM) section; and

one or more second processors each comprising a read only memory (ROM) section and a second RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.

2. The apparatus according to claim 1, wherein said one or more first processors each comprise a master processor and said one or more second processors each comprise slave processors.

3. The apparatus according to claim 1, wherein said one or more second processors execute code stored in at least one of said one or more first processors.

4. The apparatus according to claim 1, wherein said at least one of said one or more first processors processes application specific code.

5. The apparatus according to claim 4, wherein said application specific code is stored in said one or more RAM sections.

6. The apparatus according to claim 1, wherein said one or more slave processors process fixed code.

7. The apparatus according to claim 6, wherein said fixed code is stored in said ROM sections.

8. The apparatus according to claim 1, wherein at least one of said one or more first processors processes application specific code and said one or more second processors process fixed code, wherein said one or more second processors are configured to read said application specific code.

9. The apparatus according to claim 8, wherein said one or more first processors and said one or more second processors operate in one of a plurality of addressing modes.

10. The apparatus according to claim 8, wherein said one or more first processors and said one or more second processors operate in a memory mapped hardware control mode.

11. The apparatus according to claim 8, further comprising:

a plurality of address spaces each specific to a portion of said one or more first processors or a portion of said one or more second processors.

12. The apparatus according to claim 1, further comprising:

a logic circuit coupled to at least one of said one or more first processors and said one or more second processors.

13. The apparatus according to claim 1, wherein at least one of said one or more first processors is further configured to notify said one or more second processors after a reset.

14. The apparatus according to claim 13, wherein said notification determines which code is executed.

15. An apparatus comprising:

means for processing code comprising one or more first processors each comprising a Random Access Memory (RAM) section; and

means for processing code comprising one or more second processors each comprising a Read Only Memory (ROM) section and a RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.

16. A method for implementing interaccessable processors, comprising the steps of:

(A) processing code comprising one or more first processors each comprising a Random Access Memory (RAM) sections; and

(B) processing code comprising one or more second processors each comprising a Read Only Memory (ROM) section and a RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.

17. The method according to claim 16, wherein (i) step (A) further comprises processing application specific code and (ii) step (B) further comprises processing fixed code, wherein step (B) is further configured to read said application specific code.

18. The method according to claim 16, wherein step (A) and step (B) are further configured to operate in one of a plurality of addressing modes.

19. The method according to claim 16, wherein step (A) and step (B) are further configured to operate in a memory mapped hardware control mode.

20. The method according to claim 16, further comprising the step of:

(C) providing a plurality of address spaces each specific to a first portion of said one or more first processors or a second portion of said one or more second processors.