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Master/slave processor memory inter accessability in an integrated embedded system

  • US 6,604,189 B1
  • Filed: 05/22/2000
  • Issued: 08/05/2003
  • Est. Priority Date: 05/22/2000
  • Status: Expired due to Fees
First Claim
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1. An apparatus comprising:

  • one or more first processors each comprising a first random access memory (RAM) section; and

    one or more second processors each comprising a read only memory (ROM) section and a second RAM section, wherein said one or more first processors are each configured to operate in either (i) a first mode that executes code stored in said one or more ROM sections or (ii) a second mode that processes code stored in said one or more first RAM sections.

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