Accelerated thermal stress cycle test

• US 6,604,853 B2
• Filed: 10/11/2001
• Issued: 08/12/2003
• Est. Priority Date: 10/11/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liao, Keng-Hui, Lee, Wi William, Yang, Sen-Shan, Chao, Ying-Chen
• Primary Examiner(s): Gutierrez, Diego
• Assistant Examiner(s): PRUCHNIC, STANLEY J
• Application Number:
  US09/976,995
• Publication Number:
  US 20030072350A1
• Time in Patent Office: 670 Days
• Field of Search: 374/57, 374/5, 374/47, 374/45, 324/760, 324/765, 324/537, 427/124, 438/14, 438/18, 165/201, 165/267, 165/65, 738/656, 414/935
• US Class Current: 374/57
• CPC Class Codes: G01N 3/60 Investigating resistance of materials, e.g. refractory materials, to rapid heat changes thermal testing of structures or apparatus G01M99/002
• CPC Class Codes: G01N 33/0095 Semiconductive materials

Abstract

An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350° C. in an inert gas in about 2 min., and then cooled down to not higher than 70° C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

Claims

1. An accelerated thermal stress cycle test comprising the steps of:

providing a cluster of reaction chambers including at least one chemical vapor deposition (CVD) chamber and at least one cool-down chamber;

heating a pre-processed wafer to at least 350°

C. in less than 2 minutes by positioning said wafer in one of said at least one CVD chambers in an inert gas;

cooling said pre-processed wafer to a temperature not higher than 70°

C. in less than 30 seconds by moving said wafer from said at least one CVD chamber to one of said at least one cool-down chambers;

repeating sequentially said heating and cooling steps for at least three times; and

determining any defect caused by said repeated heating and cooling steps.

2. An accelerated thermal stress cycle test according to claim 1, wherein said cluster of reaction chambers having a LPCVD chamber and a cool-down chamber.

3. An accelerated thermal stress cycle test according to claim 1, wherein said at least one CVD chamber is a single wafer LPCVD chamber comprising heating lamps.

4. An accelerated thermal stress cycle test according to claim 1, wherein said at least one CVD chamber is a single wafer LPCVD chamber comprising heating means for heating a wafer from 23°

C. to 350°

C. within 2 minutes.

5. An accelerated thermal stress cycle test according to claim 1, wherein said at least one CVD chamber is a single wafer LPCVD chamber comprising heat means for heating a wafer from 23°

C. to 350°

C. within 2 minutes in an inert gas environment.

6. An accelerated thermal stress cycle test according to claim 1, wherein said at least one CVD chamber is a single wafer LPCVD chamber comprising heating means for heating a wafer from 23°

C. to 350°

C. within 2 minutes in an inert gas environment on N₂, He or Ar.

7. An accelerated thermal stress cycle test according to claim 1 further comprising the step of moving said pre-processed wafer from one of said at least one CVD chamber to one of said at least on cool-down chamber by a robot blade.

8. An accelerated thermal stress cycle test according to claim 1 further comprising the step of repeating sequentially said heating and cooling steps between 3 and 10 times.

9. An accelerated thermal stress cycle test according to claim 1, further comprising the step of repeating sequentially said heating and cooling steps for 7 times.

10. A thermal stress cycle test comprising the steps of:

providing a heating chamber and a cooling chamber positioned juxtaposed to each other, said heating chamber being a single-wafer LPCVD chamber;

positioning a preprocessed wafer in said heating chamber and heating said pre-processed wafer from 23°

C. to at least 350°

C. in less than 2 minutes;

positioning said pre-processed wafer in said cooling chamber and cooling said pre-processed wafer from 350°

C. to not higher than 70°

C. in less than 30 seconds;

repeating sequentially said heating and cooling steps for at least 3 times; and

determining any defect formed on said pre-processed wafer.

11. A thermal stress cycle test according to claim 10 further comprising the step of transporting said pre-processed wafer from said heating chamber to said cooling chamber by a robot blade.

12. A thermal stress cycle test according to claim 10 further comprising the step of providing a cluster of reaction chambers that includes said heating chamber and said cooling chamber.

13. A thermal stress cycle test according to claim 10 further comprising the step of providing said heating chamber in a chamber equipped with heating lamps.

14. A thermal stress cycle test according to claim 10 further comprising the step of flowing an inert gas selected from the group consisting of N₂, He and Ar into said heating and cooling chambers.

15. A thermal stress cycle test according to claim 10 further comprising the step of flowing N₂ into said heating chamber during the heating cycle.

16. A thermal stress cycle test according to claim 10 further comprising the step of repeating sequentially said heating and cooling steps for at least 7 times.

17. A thermal stress cycle test according to claim 10 further comprising the step of determining any peeling of a Cu layer from a dielectric material layer.

18. A thermal stress cycle test according to claim 10 further comprising the step of repeating sequentially said heating and cooling steps between 3 times and 10 times.