Semiconductor device with both memories and logic circuits and its manufacture

• US 6,605,510 B2
• Filed: 06/06/2002
• Issued: 08/12/2003
• Est. Priority Date: 03/01/2000
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Watatani, Hirofumi
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): VESPERMAN, WILLIAM C
• Application Number:
  US10/162,580
• Publication Number:
  US 20020185662A1
• Time in Patent Office: 432 Days
• Field of Search: 257/368, 438/304, 438/311, 438/379, 438/275, 438/276
• US Class Current: 438/275
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and extends to the surface of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.

Claims

1. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming an element separation insulating film on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film;

(b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode;

(c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask;

(d) covering the first gate lamination structure with a first film made of insulating material;

(e) forming a second film on the first film, the second film being made of insulating material having an etching resistance different from an etching resistance of the first film;

(f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films;

(g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask;

(h) selectively removing the second film of the two layers constituting the first side wall spacer;

(i) forming metal silicide films on surfaces of regions where the impurities were implanted by said implanting step (g); and

(j) forming an interlayer insulating film covering the first gate lamination structure and the metal silicide films.

2. A method of manufacturing a semiconductor device according to claim 1, wherein:

said step (a) includes a step of defining a second active region in an area different from the first active region;

said step (b) includes a step of forming a second gate lamination structure having a same structure as the first gate lamination structure, on a partial surface area of the second active region;

said step (c) includes a step of implanting impurities in surface layers of the semiconductor substrate on both sides of the second gate lamination structure, by using the second gate lamination structure as a mask;

said step (d) includes a step of covering the second gate lamination structure with the first film;

said step (f) includes a step of covering the second film in the second active region with a mask pattern and a step of anisotropically etching the first and second films in an area not covered with the mask pattern;

the method further comprises a step of removing the mask pattern before said step (h);

the second film in the second active region is also removed by said step (h); and

in said step (j), the second gate lamination structure is also covered with the interlayer insulating film.

3. A method of manufacturing a semiconductor device according to claim 2 wherein said first active region is located in a logic circuit area and said second active region is located in a memory cell area.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the element separation insulating film is made of silicon oxide and the second film is made of a material selected from a group consisting of phosphosilicate glass, borosilicate glass and borophosphosilicate glass.

5. A method of manufacturing a semiconductor device according to claim 1, wherein the element separation insulating film is formed by CVD using O₂ and SiH₄, and the second film is formed by CVD using O₃ and TEOS.

6. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming an element separation insulating film made of silicon oxide on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film;

(b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode;

(c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask;

(d) covering the first gate lamination structure with a first film made of insulating material having an etching resistance different from an etching resistance of silicon oxide;

(e) forming a second film made of silicon oxide on the first film;

(f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films;

(g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask;

(h) selectively removing the second film of the two layers constituting the first side wall spacer;

(i) forming a metal silicide film on surfaces of regions where the impurities were implanted by said second impurity implanting step; and

(j) forming an interlayer insulating film covering the first gate lamination structure and metal silicide films.

7. A method of manufacturing a semiconductor device according to claim 6, wherein

said step (a) includes a step of defining a second active region in an area different from the first active region;

said step (b) includes a step of forming a second gate lamination structure having a same structure as the first gate lamination structure, on a partial surface area of the second active region;

said step (c) includes a step of implanting impurities in surface layers of the semiconductor substrate on both sides of the second gate lamination structure, by using the second gate lamination structure as a mask;

said step (d) includes a step of covering the second gate lamination structure with the first film;

said step (f) includes a step of covering the second film in the second active region with a mask pattern and a step of anisotropically etching the first and second films in an area not covered with the mask pattern;

the method further comprises a step of removing the mask pattern before said step (h);

the second film in the second active region is also removed by said step (h); and

in said step (j), the second gate lamination structure is also covered with the interlayer insulating film.

8. A method of manufacturing a semiconductor device according to claim 7, wherein said first active region is located in a logic circuit area and said second active region is located in a memory cell area.

9. A method of manufacturing a semiconductor device according to claim 6, wherein the second film is made of silicon oxide containing phosphorous or boron.