Process to control etch profiles in dual-implanted silicon films
First Claim
1. A method for selectively etching a gate stack having a silicon layer covering a thin oxide layer which covers a substrate, the silicon layer having an anti-reflective coating layer thereon comprising:
- etching through the anti-reflective coating layer of the gate stack, with a first process gas having a fluorine-based chemistry, until the silicon layer is exposed;
etching the silicon layer of the gate stack with a second process gas including a mixture of HBr, Cl2, and CF4;
etching the gate stack with a third process gas including a mixture of HBr,Cl2 and 80% He—
O2 until the thin oxide is exposed; and
over etching the gate stack with a fourth process gas including a mixture of HBr, 80% He—
O2 and He.
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Abstract
A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack. Formation of micro-trenches, while achieving nearly vertical profiles, is substantially minimized. In a method for manufacturing a semiconductor device gate stack a breakthrough etch removes residual oxide and anti-reflection coating until the layer of amorphous silicon is exposed. A bulk etch removes the amorphous silicon until about 40% remains. The remaining amorphous silicon layer is etched with a high selectivity etch until oxide is exposed. Any residual poly or amorphous silicon is etched with a very high-selectivity ratio over etch until clear.
20 Citations
13 Claims
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1. A method for selectively etching a gate stack having a silicon layer covering a thin oxide layer which covers a substrate, the silicon layer having an anti-reflective coating layer thereon comprising:
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etching through the anti-reflective coating layer of the gate stack, with a first process gas having a fluorine-based chemistry, until the silicon layer is exposed;
etching the silicon layer of the gate stack with a second process gas including a mixture of HBr, Cl2, and CF4;
etching the gate stack with a third process gas including a mixture of HBr,Cl2 and 80% He—
O2 until the thin oxide is exposed; and
over etching the gate stack with a fourth process gas including a mixture of HBr, 80% He—
O2 and He.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
wherein the second process gas mixture of HBr, Cl2, and CF4 has gas flow ratios of about (80-100): - (13-17);
(11-13) HBr;
Cl2;
CF4.
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5. The method of claim 1,
wherein the third process gas mixture of HBr,Cl2 and 80% He— - O2 has gas flow ratios of about (135-165);
(8-11);
(13-17) HBr;
Cl2;
80% He—
O2 until the thin oxide is exposed.
- O2 has gas flow ratios of about (135-165);
-
6. The method of claim 1,
wherein the fourth process gas mixture of HBr, 80% He— - O2 and;
He, has gas flow ratios of about (180-220);
(8-12);
(180-200) HBr;
80% He—
O2;
He.
- O2 and;
-
7. The method of claim 1,
wherein the second process gas mixture of HBr, Cl2, and CF4 has gas flow ratios of about (80-100): - (13-17);
(11-13) HBr;
Cl2;
CF4;
wherein the third process gas mixture of HBr,Cl2 and 80% He—
O2 has gas flow ratios of about (135-165);
(8-11);
(13-17) HBr;
Cl2;
80% He—
O2; and
wherein the fourth process gas mixture of HBr, 80% He—
O2 and;
He, has gas flow ratios of about (180-220);
(8-12);
(180-200) HBr;
80% He—
O2;
He.
- (13-17);
-
8. The method of claim 1 wherein the first process gas is selected from the group including CF4, NF3 and SF6.
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9. The method of claim 1 wherein the first process gas has a flow rate in the range of about 80 to 120 sccm.
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10. The method of claim 1 wherein the third process gas has a silicon-to-gate oxide selectivity ratio of at least 140:
- 1.
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11. The method of claim 1 wherein the gate stack is etched to a profile in the range of about 85°
- to 90°
.
- to 90°
-
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12. A method for etching unmasked areas of a gate stack having an anti reflective coating layer formed on a doped silicon layer on a silicon oxide on a substrate, comprising:
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placing the substrate into an etch chamber;
etching the anti reflective coating layer with a breakthrough etch until the silicon layer is exposed;
etching the silicon layer with a bulk etch until about 40% of the silicon layer remains;
etching the remaining silicon layer with a high-selectivity etch including Cl2, HBr, and 80% He—
O2 introduced into the etch chamber at flow rates in ranges of about 8-12 sccm, 120-180 sccm, and 12-18 sccm, respectively until the silicon oxide is exposed; and
over-etching the remaining silicon layer with a very high-selectivity etch until silicon residues are cleared.
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13. A method for etching unmasked areas of a gate stack having an anti reflective coating layer formed on a doped silicon layer on a silicon oxide on a substrate, comprising:
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placing the substrate into an etch chamber;
etching the anti reflective coating layer with a breakthrough etch including CF4 introduced into, the etch chamber at a flow rate in the range of about 80 sccm to 120 sccm until the silicon layer is exposed;
etching the silicon layer with a bulk etch including Cl2, HBr, and CF4 introduced into the etch chamber at flow rates in ranges of about 12-18 sccm, 70-110 sccm, and 9-15 sccm, respectively until about 40% of the silicon layer remains;
etching the remaining silicon layer with a high-selectivity etch including Cl2, HBr, and 80% He—
O2 introduced into the etch chamber at flow rates in ranges of about 8-12 sccm, 120-180 sccm, and 12-18 sccm, respectively until the silicon oxide is exposed; and
over-etching the remaining silicon layer with a very high-selectivity etch including HBr, and 80% He—
O2, and He introduced into the etch chamber at flow rates in ranges of about 160-240 sccm, 8-12 sccm, and 160-240 sccm, respectively until silicon residues are cleared.
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Specification