Trench semiconductor devices

• US 6,605,862 B2
• Filed: 02/07/2002
• Issued: 08/12/2003
• Est. Priority Date: 02/22/2001
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Dalen, Rob, Hurkx, Godefridus A. M., Rochefort, Christelle
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/068,921
• Publication Number:
  US 20020130358A1
• Time in Patent Office: 551 Days
• Field of Search: 257/621, 162/2
• US Class Current: 257/621
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41). This lower level (82) is more closely aligned to the p-n junction (24) and is protected by the insulating layer (44) extending to the higher level (81). This construction enables the electric field distribution in the voltage-sustaining zone (20) to be improved by aligning very closely the start of the potential drop along the resistive path (42) with the p-n junction depth (d).

Claims

1. A semiconductor device comprising a semiconductor body in which a p-n junction is formed between a first device region of one conductivity type and an underlying voltage-sustaining zone, wherein a trenched field-shaping region extends in a trench through the voltage-sustaining zone to an underlying second device region, the trench extends from an upper surface of the body through the first device region and the voltage-sustaining zone, the trench accommodates a resistive path of semi-insulating material that is connected between the second device region and a device electrode that contacts the first device region, the resistive path starting below the level of the upper surface of the body, an insulating layer is present at side-walls of the trench to dielectrically couple potential from the resistive path to the voltage-sustaining zone, the first device region extending laterally to the insulating layer, and the voltage-sustaining zone is so dimensioned and doped between the trenched field-shaping regions as to be depleted of free charge carriers between the trenched field-shaping regions in a voltage-blocking mode of operation of the device by the spread of a depletion layer from the p-n junction, the device being characterized in that the insulating layer extends at the side-walls of the trench to an upper level that is higher than a lower level at which the resistive path starts in the trench, which lower level is more closely aligned to the depth of the p-n junction in the body and is protected by the insulating layer, and in that the semi-insulating material extends to the upper level in the trench but is highly doped with conductive dopant between the upper and lower levels so as to form a terminal region of the resistive path, and in that the device electrode that contacts the first device region also contacts this terminal region of the resistive path.

2. A device according to claim 1, further characterized in that the semi-insulating material is absent above the lower level in the trench, and the device electrode that contacts the first device region extends into the upper part of the trench to contact the resistive path at this lower level.

3. A device according to claim 1, further characterized in that the lower level is close to but slightly below the depth to which the p-n junction extends in the body.

4. A device according to claim 1, further characterized in that the first device region is a transistor body region of an insulated gate field-effect transistor, the device electrode that contacts the first device region is a source electrode that also contacts a source region of opposite conductivity type, and an insulated gate electrode is coupled to the transistor body region for controlling a conduction channel in an on-state of the transistor between the source region and the underlying voltage-sustaining zone that provides a drain drift region of the transistor.

5. A device according to claim 4, further characterized in that the upper level to which the insulating layer extends is below the upper surface of the body, and in that the source electrode extends into the upper part of the trench to contact both the transistor body region and the source region at the side-wall of the trench and to contact the resistive path at the lower level in the trench.

6. A device according to claim 5, further characterized in that the insulated gate electrode is a trench-gate structure that is located in between trenches of the trenched field-shaping regions, and in that the source region extends laterally from an insulated side-wall of the trench-gate structure to the side-wall of the neighbouring trench of the trenched field-shaping regions.

7. A device according to claim 1, further characterized in that the upper level to which the insulating layer extends coincides substantially with the upper surface of the body.

8. A device according to claim 1, further characterized in that the resistive path of the trenched field-shaping regions comprises a layer of the semi-insulating material on the insulating layer at the side-walls of the trench, and in that an insulating filler material is present on the layer of the semi-insulating material to fill the remainder of the trench to a desired level.

9. A device according to claim 8, further characterized in that the insulating filler material is selectively etchable with respect to the insulating layer at the side-walls of the trench, and in that the insulating filler material fills the remainder of the trench to a lower level than the height to which the layer of the semi-insulating material extends.

10. A device according to claim 1, further characterized in that voltage sustaining zone comprises a region of the opposite conductivity type that is separated from the insulating layer at the side walls of the trench by a side-wall region of the one conductivity type, and the p-n junction extends laterally to said side-wall region.

11. A device according to claim 1, further characterized in that the p-n junction extends laterally to meet the insulating layer at the side wall of the trench.