Method of making semiconductor device using an interconnect

• US 6,605,874 B2
• Filed: 12/19/2001
• Issued: 08/12/2003
• Est. Priority Date: 12/19/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thomas, Christopher D., Leu, Jihperng
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/025,030
• Publication Number:
  US 20030111729A1
• Time in Patent Office: 601 Days
• Field of Search: 257/758, 438/118, 438/622
• US Class Current: 257/758
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.

Claims

1. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a first recess;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is disposed in an upper recess;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a nitride barrier film disposed in at least one of the first recess and in the upper recess; and

a conductive diffusion barrier film disposed over at least one of the nitride barrier film.

6. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CuB, CuBP, CuCrB, CuCrBP, CuMoB, CuMoBP, CuWB, CuWBP, CuMnB, CuMnBP, CuTcB, CuTcBP, CuReB, CuReBP, CuNiB, CuNiBP, CuNiCrB, CuNiCrBP, CuNiMoB, CuNiMoBP, CuNiWB, CuNiWBP, CuNiMnB, CuNiMnBP, CuNiTcB, CuNiTcBP, CuNiReB, and CuNiReBP.

7. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from NiB, NiBP, NiCrB, NiCrBP, NiMoB, NiMoBP, NiWB, NiWBP, NiMnB, NiMnBP, NiTcB, NiTcBP, NiReB, NiReBP, NiCoB, NiCoBP, NiCoCrB, NiCoCrBP, NiCoMoB, NiCoMoBP, NiCoWB, NiCoWBP, NiCoMnB, NiCoMnBP, NiCoTcB, NiCoTcBP, NiCoReB, and NiCoReBP.

8. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CoB, CoBP, CoCrBP CoCrBP, CoMoB, CoMoBP, CoWB, CoWBP, CoMnB, CoMnBP, CoTcB, CoTcBP, CoReB, CoReBP, NiCoB, CoPdBP, CoPdCrB, CoPdCrBP, CoPdMoB, CoPdMoBP, CoPdWB, CoPdWBP, CoPdMnB, CoPdMnBP, CoPdTcB, CoPdTcBP, CoPdReB, and CoPdReBP.

9. In the microelectronic device, the article according to claim 1, wherein the first interconnect is disposed in a first recess, wherein the upper interconnect is disposed in an upper recess, further including:

a nitride barrier film disposed in at least one of the first recess and in the upper recess; and

a conductive seed film disposed over the nitride barrier film.

10. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CuB, CuBP, CuCrB, CuCrBP, CuMoB, CuMoBP, CuWB, CuWBP, CuMnB, CuMnBP, CuTcB, CuTcBP, CuReB, CuReBP, CuNiB, CuNiBP, CuNiCrB, CuNiCrBP, CuNiMoB, CuNiMoBP, CuNiWB, CuNiWBP, CuNiMnB, CuNiMnBP, CuNiTcB, CuNiTcBP, CuNiReB, and CuNiReBP, and wherein Cu is substituted by at least one of Ag and Au.

11. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CuB, CuBP, CuCrB, CuCrBP, CuMoB, CuMoBP, CuWB, CuWBP, CuMnB, CuMnBP, CuTcB, CuTcBP, CuReB, CuReBP, CuNiB, CuNiBP, CuNiCrB, CuNiCrBP, CuNiMoB, CuNiMoBP, CuNiWB, CuNiWBP, CuNiMnB, CuNiMnBP, CuNiTcB, CuNiTcBP, CuNiReB, and CuNiReBP, and wherein Cu is accompanied by at least one of Ag and Au.

12. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from NiB, NiBP, NiCrB, NiCrBP, NiMoB, NiMoBP, NiWB, NiWBP, NiMnB, NiMnBP, NiTcB, NiTcBP, NiReB, NiReBP, NiCoB, NiCoBP, NiCoCrB, NiCoCrBP, NiCoMoB, NiCoMoBP, NiCoWB, NiCoWBP, NiCoMnB, NiCoMnBP, NiCoTcB, NiCoTcBP, NiCoReB, and NiCoReBP, and wherein Ni is substituted by at least one of Pd and Pt.

13. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from NiB, NiBP, NiCrB, NiCrBP, NiMoB, NiMoBP, NiWB, NiWBP, NiMnB, NiMnBP, NiTcB, NiTcBP, NiReB, NiReBP, NiCoB, NiCoBP, NiCoCrB, NiCoCrBP, NiCoMoB, NiCoMoBP, NiCoWB, NiCoWBP, NiCoMnB, NiCoMnBP, NiCoTcB, NiCoTcBP, NiCoReB, and NiCoReBP, and wherein Ni is accompanied by at least one of Pd and Pt.

14. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CoB, CoBP, CoCrB, CoCrBP, CoMoB, CoMoBP, CoWB, CoWBP, CoMnB, CoMnBP, CoTcB, CoTcBP, CoReB, CoReBP, NiCoB, CoPdBP, CoPdCrB, CoPdCrBP, CoPdMoB, CoPdMoBP, CoPdWB, CoPdWBP, CoPdMnB, CoPdMnBP, CoPdTcB, CoPdTcBP, CoPdReB, and CoPdReBP, and wherein Co is substituted by at least one of Rh and Ir.

15. In the microelectronic device, the article according to claim 1, wherein at least one of the conductive diffusion barrier layers or films is selected from CoB, CoBP, CoCrB, CoCrBP, CoMoB, CoMoBP, CoWB, CoWBP, CoMnB, CoMnBP, CoTcB, CoTcBP, CoReB, CoReBP, NiCoB, CoPdBP, CoPdCrB, CoPdCrBP, CoPdMoB, CoPdMoBP, CoPdWB, CoPdWBP, CoPdMnB, CoPdMnBP, CoPdTcB, CoPdTcBP, CoPdReB, and CoPdReBP, and wherein Co is accompanied by at least one of Rh and Ir.

2. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a recess in an organic interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is a second interconnect that is disposed above and on the first conductive diffusion barrier layer, wherein the second interconnect is disposed in an inorganic dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect; and

a hard mask disposed over the organic interlayer dielectric layer wherein the hard mask includes an opening that defines a characteristic dimension of the first interconnect.

3. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a recess in a first interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is a second interconnect that is disposed above and on the first conductive diffusion barrier layer, wherein the second interconnect is disposed in a second interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the first interlayer dielectric layer wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

a second hard mask disposed over the second interlayer dielectric layer wherein the second hard mask includes an opening that defines a characteristic dimension of the second interconnect.

4. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a first recess including an inorganic first bottom interlayer dielectric layer and an organic first top interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is disposed in an upper recess including an inorganic upper bottom interlayer dielectric layer and an organic upper top interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the first top interlayer dielectric layer, wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

an upper hard mask disposed over the upper top interlayer dielectric layer, wherein the upper hard mask includes an opening that defines a characteristic dimension of the upper interconnect.

5. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a first recess including an organic first bottom interlayer dielectric layer and an inorganic first top interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is disposed in an upper recess including an organic upper bottom interlayer dielectric layer and an inorganic upper top interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the organic first bottom interlayer dielectric layer, wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

an upper hard mask disposed over the organic upper bottom interlayer dielectric layer, wherein the upper hard mask includes an opening that defines a characteristic dimension of the upper interconnect.

16. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a first recess, wherein the first recess is covered with a first conductive diffusion barrier film;

a first conductive diffusion barrier layer disposed above and on the first interconnect, wherein the first conductive diffusion barrier film optionally includes substantially the same material as the first conductive diffusion barrier layer,

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is disposed in an upper recess, wherein the upper recess is covered with a upper conductive diffusion barrier film;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect wherein the upper conductive diffusion barrier film optionally includes substantially the same material as the upper conductive diffusion barrier layer.

17. The article according to claim 16, wherein at least one of the first- and upper conductive diffusion barrier layer is a metal or alloy selected from at least one of copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, chromium, molybdenum, tungsten, manganese, technetium, rhenium cobalt-nickel, cobalt-nickel-silver, cobalt-nickel-silver-copper, cobalt-silver, cobalt-silver-copper, cobalt-copper, cobalt-copper-nickel, nickel-silver, nickel-silver-copper, nickel-copper, and silver-copper.

18. The article according to claim 16, wherein the first interconnect is disposed in a first recess, wherein the upper interconnect is disposed in an upper recess, further including:

a nitride barrier film disposed in at least one of the first recess and in the upper recess; and

a conductive seed film disposed over the nitride barrier film.

19. The article according to claim 16, wherein at least one of the conductive diffusion barrier layers or films is selected from CuB, CuBP, CuCrB, CuCrBP, CuMoB, CuMoBP, CuWB, CuWBP, CuMnB, CuMnBP, CuTcB, CuTcBP, CuReB, CuReBP, CuNiB, CuNiBP, CuNiCrB, CuNiCrBP, CuNiMoB, CuNiMoBP, CuNiWB, CuNiWBP, CuNiMnB, CuNiMnBP, CuNiTcB, CuNiTcBP, CuNiReB, and CuNiReBP.

20. The article according to claim 16, wherein at least one of the conductive diffusion barrier layers or films is selected from NiB, NiBP, NiCrB, NiCrBP, NiMoB, NiMoBP, NiWB, NiWBP, NiMnB, NiMnBP, NiTcB, NiTcBP, NiReB, NiReBP, NiCoB, NiCoBP, NiCoCrB, NiCoCrBP, NiCoMoB, NiCoMoBP, NiCoWB, NiCoWBP, NiCoMnB, NiCoMnBP, NiCoTcB, NiCoTcBP, NiCoReB, and NiCoReBP.

21. The article according to claim 16, wherein at least one of the conductive diffusion barrier layers or films is selected from CoB, CoBP, CoCrB, CoCrBP, CoMoB, CoMoBP, CoWB, CoWBP, CoMnB, CoMnBP, CoTcB, CoTcBP, CoReB, CoReBP, NiCoB, CoPdBP, CoPdCrB, CoPdCrBP, CoPdMoB, CoPdMoBP, CoPdWB, CoPdWBP, CoPdMnB, CoPdMnBP, CoPdTcB, CoPdTcBP, CoPdReB, and CoPdReBP.

22. In a microelectronic device, an article comprising:

a first interconnect disposed above a substrate, wherein the first interconnect is disposed in a first recess;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect;

wherein the upper interconnect is disposed in an upper recess;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a nitride barrier film disposed in at least one of the first recess and in the upper recess;

a conductive diffusion barrier film disposed over at least one of the nitride barrier film; and

a conductive seed film disposed over the nitride barrier film.

23. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a first recess;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is disposed in an upper recess;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a nitride barrier film disposed in at least one of the first recess and in the upper recess;

a conductive diffusion barrier film disposed over at least one of the nitride barrier film; and

a conductive seed film disposed over the conductive diffusion barrier film.

24. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a first recess, wherein the first recess is covered with a first conductive diffusion barrier film;

a first conductive diffusion barrier layer disposed above and on the first interconnect, wherein the first conductive diffusion barrier film includes substantially the same material as the first conductive diffusion barrier layer;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is disposed in an upper recess, wherein the upper recess is covered with an upper conductive diffusion barrier film; and

an upper conductive diffusion barrier layer disposed above and on the upper interconnect wherein the upper conductive diffusion barrier film includes substantially the same material as the upper conductive diffusion barrier layer.

25. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a recess in a first interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect;

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is a second interconnect that is disposed above and on the first conductive diffusion barrier layer, wherein the second interconnect is disposed in a second interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the first interlayer dielectric layer wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

a second hard mask disposed over the second interlayer dielectric layer wherein the second hard mask includes an opening that defines a characteristic dimension of the second interconnect.

26. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a first recess including an inorganic first bottom interlayer dielectric layer, and an organic first top interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect,

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is disposed in an upper recess including an inorganic upper bottom interlayer dielectric layer, and an organic upper top interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the first top interlayer dielectric layer, wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

an upper hard mask disposed over the upper top interlayer dielectric layer, wherein the upper hard mask includes an opening that defines a characteristic dimension of the upper interconnect.

27. An article comprising:

a first interconnect disposed above a semiconductor substrate that includes at least one active device, wherein the first interconnect is disposed in a first recess including an organic first bottom interlayer dielectric layer, and an inorganic first top interlayer dielectric layer;

a first conductive diffusion barrier layer disposed above and on the first interconnect,

an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect, wherein the upper interconnect is disposed in an upper recess including an organic upper bottom interlayer dielectric layer, and an inorganic upper top interlayer dielectric layer;

an upper conductive diffusion barrier layer disposed above and on the upper interconnect;

a first hard mask disposed over the organic first bottom interlayer dielectric layer, wherein the first hard mask includes an opening that defines a characteristic dimension of the first interconnect; and

an upper hard mask disposed over the organic upper bottom interlayer dielectric layer, wherein the upper hard mask includes an opening that defines a characteristic dimension of the upper interconnect.