True background calibration of pipelined analog digital converters

• US 6,606,042 B2
• Filed: 05/23/2002
• Issued: 08/12/2003
• Est. Priority Date: 05/23/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc., University of Pennsylvania
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sonkusale, Sameer, Van der Spiegel, Jan, Nagaraj, Krishnasawamy
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US10/154,358
• Publication Number:
  US 20020175843A1
• Time in Patent Office: 446 Days
• Field of Search: 341/120, 341/118, 341/122, 341/155, 341/156, 341/172, 341/161
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1004 without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated H03M1/1009, H03M1/1071 take precedence
• CPC Class Codes: H03M 1/1033 over the full range of the converter, e.g. for correcting differential non-linearity
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

Systems and methods are provided for performing a background calibration technique on one or more stages of a pipeline Analog-to-Digital Converter (ADC). The systems and methods employs a slow but accurate analog-to-digital converter or a slow but accurate ideal pipeline stage to correct for the residue errors in a non-ideal pipeline stage using an error function and a correction algorithm. The correction algorithm determines optimal parameters of the error function, so that the error function can be utilized to compensate for errors in the ADC. The correction algorithm and results can be applied in the digital domain or in the analog domain.

Claims

1. A system for calibrating a pipeline Analog-to-Digital converter (ADC), the system comprising:

an ideal pipeline stage that receives an input voltage of a pipeline stage and provides an ideal residue voltage;

an error function that receives a residue voltage of the pipeline stage and provides a residue voltage estimate; and

a correction algorithm that optimizes at least one parameter associated with the error function, so that the residue voltage estimate is approximately equal to the ideal residue voltage.

2. The system of claim 1, the correction algorithm executes a gradient-descent least mean square approach to optimize the at least one parameter.

3. The system of claim 1, the correction algorithm optimizes a first parameter that represents the capacitor mismatch and finite operational amplifier gain error of the stage and a second parameter that represents the offset of the stage.

4. The system of claim 1, the ideal pipeline stage, the error function and the correction algorithm being employed to calibrate a plurality of stages of the pipeline ADC.

5. The system of claim 1, further comprising a plurality error functions such that each error function is associated with a single stage of the pipeline ADC, such that the ideal pipeline stage, the correction algorithm and the associated error function are employed to calibrate an associated pipeline stage.

6. The system of claim 1, the pipeline stage being a single bit per stage converter in a switched capacitor configuration.

7. The system of claim 1, the error function with the at least one optimized parameter maps the actual residue voltage to the ideal residue voltage to compensate for errors associated with the pipeline stage.

8. The system of claim 1, further comprising a switch that switches a calibrated residue voltage from the error function to the pipeline stage output.

9. The system of claim 1, the error function with the at least one optimized parameter is applied in the analog domain.

10. The system of claim 9, the at least one optimized parameter being a first parameter that represents the capacitor mismatch and finite operational amplifier gain error of the stage and a second parameter that represents the offset of the stage, the first parameter determines a value of a variable reference voltage to be applied to the stage and the second parameter determines an amount of charge to be discharged through a trimming capacitor.

11. The system of claim 1, the error function with the at least one optimized parameter is applied in the digital domain.

12. A system for calibrating a pipeline Analog-to-Digital converter (ADC) having a plurality of pipeline stages, the system comprising:

a calibrator comprising an ideal pipeline stage that receives an input voltage of a pipeline stage, and an error function correction component that receives a residue voltage of the pipeline stage, the ideal pipeline stage provides an ideal residue voltage to the error correction component which optimizes at least one parameter associated with an error function that can be applied to the pipeline stage to compensate for errors associated with the pipeline stage; and

a switch bank that switches the calibrator amongst the plurality of stages for performing calibration associated with a respective stage.

13. The system of claim 12, the calibrator calibrates the plurality of stages in order from the least significant bits to the most significant bits of the pipeline ADC.

14. The system of claim 13, the calibrator eliminates calibration at stages where the error impact due to capacitor mismatches and finite operational amplifier gain error is insignificant.

15. The system of claim 12, the pipeline ADC being an 8-bit pipeline ADC.

16. The system of claim 15, further comprising at least one dummy stage to facilitate the accuracy of calibration of the pipeline ADC.

17. The system of claim 12, the error correction component executes a gradient-descent least mean square approach to optimize the at least one parameter.

18. The system of claim 12, the calibrator determining the digital word equivalent of the ideal residue for each stage calibrated.

19. A system for calibrating a pipeline Analog-to-Digital converter (ADC), the system comprising:

means for determining an ideal residue voltage from an input voltage of a pipeline stage;

means for providing a residue voltage estimate of an error function; and

means for optimizing at least one parameter associated with the error function, so that the residue voltage estimate is approximately equal to the ideal residue voltage.

20. The system of claim 19, further comprising means for applying the error function and the at least one optimized parameter to compensate for errors associated with the pipeline stage.

21. The system of claim 20, the means for applying the error function and the at least one optimized parameter being applied in the analog domain.

22. The system of claim 20, the means for applying the error function and the at least one optimized parameter being applied in the digital domain.

23. A background calibration method for calibrating a pipeline Analog-to-Digital Converter (ADC), the method comprising:

sampling an input signal to a pipeline stage;

determining an ideal residual voltage of the pipeline stage;

providing an initial residual voltage estimate of an error function;

executing a correction algorithm to optimize at least one parameter of the error function; and

applying the error function with the at least one optimized parameter to the pipeline stage to correct for errors associated with the pipeline stage.

24. The method of claim 23, the executing a correction algorithm comprising executing a gradient-descent least mean square routine to optimize the at least one parameter until the estimated residual voltage is approximately equal to the ideal residual voltage.

25. The method of claim 24, the at least one parameter being a first parameter representing the capacitor mismatch and finite operational amplifier gain error of the stage and a second parameter representing the offset of the stage.

26. The method of claim 23, the applying the error function with the at least one optimized parameter to correct for errors associated with the pipeline stage being applied to the actual residual voltage to provide a calibrated residual voltage.

27. The method of claim 23, the applying the error function with the at least one optimized parameter to correct for errors associated with the pipeline stage being applied to the digital output of the pipeline stage.

28. The method of claim 23, being applied to a plurality of pipeline stages forming the ADC.