Non-disturbing programming scheme for magnetic RAM

• US 6,606,263 B1
• Filed: 04/19/2002
• Issued: 08/12/2003
• Est. Priority Date: 04/19/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tang, Denny
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/126,383
• Time in Patent Office: 480 Days
• Field of Search: 365/158, 365/171, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

In magnetic RAMs a particular memory cell is selected when it is at the intersection of a row and a column of half-selected cells. When data is written into the selected cell, the associated magnetic field can sometimes disturb a neighboring half-selected cell. This restricts the current range available for programming cells. The present invention solves this problem by using two bit lines. One end of the memory cell is connected to a first bit line, in a similar manner to the prior art. However, the programming line does not extend across the full width of the array, being instead connected to a second bit line immediately after it has passed directly across the memory cell. Orthogonal to the two bit lines is a word line whose role is to activate/deactivate transistors associated with the selected cell. Both 1T1R and 2T1R versions of the invention are described.

Claims

1. A method to store and read data in a memory device, comprising:

providing a field effect transistor having a gate, a source and a drain;

providing first and second bit lines that are parallel to one another and a word line that is orthogonal to said first and second bit lines;

providing a storage element having a magnetization direction, first and second ends as well as a free layer and a pinned layer;

connecting said source to ground and said gate to said word line;

connecting said drain to a first end of said storage element through a first connecting line;

connecting said drain to said second bit line through a second connecting line that passes directly over said storage element;

connecting a second end of said storage element to said first bit line;

magnetizing said free layer in a direction by passing a current through said second connecting line;

applying a voltage between said word line and said first bit line thereby activating said field effect transistor;

while measuring current flowing through said first bit line, applying a voltage between said second bit line and ground thereby causing a current to flow through said second connecting line; and

thereby determining the magnetization direction of said free layer.

2. The method described in claim 1 wherein said storage element is a spin valve.

3. The method described in claim 1 wherein said storage element is a pseudo-spin valve.

4. The method described in claim 1 wherein said storage element is a magnetic tunnel junction device that further comprises a base layer and antiferromagnetic layer.

5. The method described in claim 4 wherein said second connecting line includes said pinned layer.

6. The method described in claim 4 wherein said second connecting line includes, said base layer, said pinned layer, and said antiferromagnetic layer.

7. A method to store and read data, comprising:

providing a first field effect transistor having a first gate, a first source and a first drain;

providing a second field effect transistor having a second gate, a second source and a second drain;

providing first and second bit lines that are parallel to one another, first and second data lines that are parallel to said bit lines and a word line that is orthogonal to said bit lines;

providing a storage element having a magnetization direction, first and second ends as well as a free layer and a pinned layer;

providing a program line, having first and second ends, that crosses said storage element;

connecting said first source to said first data line, said first gate to said word line, and said first drain to said first end of said storage element;

further connecting said first drain to said first end of said program line;

connecting said second end of said program line to said second drain;

connecting said second end of said storage element to said first bit line;

connecting said second source to said second data line;

connecting said second gate to said second bit line;

activating said word line and said second bit line, thereby turning on both field effect transistors, and passing a current from said first data line to said second data line through said program line whereby said free layer is magnetized in a direction;

applying a voltage between said first data line and said first bit line causing a current to flow through said first bit line; and

by measuring said current flowing through said first bit line, determining the magnetization direction of said free layer.

8. The method described in claim 7 wherein said storage element is a spin valve.

9. The method described in claim 7 wherein said storage element is a pseudo-spin valve.

10. The method described in claim 7 wherein said storage element is a magnetic tunneling junction device.

11. The method described in claim 10 wherein said program line further comprises said pinned layer.

12. The method described in claim 10 wherein said program line further comprises, said pinned layer, said antiferromagnetic layer, and said base layer.

13. A memory device, comprising:

a field effect transistor having a gate, a source and a drain;

first and second bit lines that are parallel to one another and a word line that is orthogonal to said first and second bit lines;

a storage element having first and second ends as well as a free layer, a longitudinal axis, and a pinned layer;

said source being connected to ground and said gate to said word line;

said drain being connected to a first end of said storage element through a first connecting line;

said drain being connected to said second bit line through a second connecting line that passes directly over, and is in contact with, the longitudinal axis of said storage element in a direction that is independent of how said second connecting line is oriented; and

a second end of said storage element being connected to said first bit line.

14. The memory device described in claim 13 wherein said storage element is a spin valve.

15. The memory device described in claim 13 wherein said storage element is a pseudo-spin valve.

16. The memory device described in claim 13 wherein said storage element is a magnetic tunnel junction device.

17. The memory device described in claim 13 wherein said transistor is an NMOS device.

18. The memory device described in claim 13 wherein said transistor is an PMOS device.

19. The memory device described in claim 13 wherein said field effect transistor is replaced by a bipolar transistor, an electro-mechanical switch, or a biological switch.

20. A memory device, comprising:

a magnetic storage element having first and second ends as well as a free layer and a pinned layer;

a first field effect transistor having a first gate, a first source and a first drain;

a second field effect transistor having a second gate, a second source and a second drain;

first and second bit lines, that are parallel to one another, and first and second data line that are parallel to said bit lines, and a word line that is orthogonal to said bit lines;

a program line, having first and second ends, that crosses said storage element;

said first source being connecting to said first data line, said first gate to said word line, and said first drain to said first end of said storage element;

said first drain being further connected to said first end of said program line;

said second end of said program line being connected to said second drain;

said second end of said storage element being connected to said first bit line;

said second source connected to said second data line; and

said second gate being connected to said second bit line.

21. The memory device described in claim 20 wherein said magnetic storage element is a spin valve.

22. The memory device described in claim 20 wherein said magnetic storage element is a pseudo-spin valve.

23. The memory device described in claim 20 wherein said storage element is a magnetic tunnel junction device that further comprises a base layer and an antiferromagnetic layer.

24. The memory device described in claim 23 wherein said second connecting line further comprises said pinned layer.

25. The memory device described in claim 23 wherein said program line further comprises, said base layer, said pinned layer, and said anti-ferromagnetic layer.

26. The memory device described in claim 20 wherein said transistor is an NMOS device.

27. The memory device described in claim 20 wherein said transistor is a PMOS device.

28. The memory device described in claim 20 wherein said first transistor is an NMOS device and said second transistor is a PMOS device.

29. The memory device described in claim 20 wherein said first transistor is a PMOS device and said second transistor is an NMOS device.

30. The memory device described in claim 20 wherein a field effect transistor is replaced by a bipolar transistor, an electro-mechanical switch, or a biological switch.