Look ahead encoder/decoder architecture

• US 6,606,328 B1
• Filed: 12/15/1999
• Issued: 08/12/2003
• Est. Priority Date: 12/15/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Susnow, Dean
• Primary Examiner(s): VANDERPUYE, KENNETH N
• Application Number:
  US09/461,394
• Time in Patent Office: 1,336 Days
• Field of Search: 341/50, 341/58, 341/51, 341/55, 370/532, 370/537, 370/477, 370/465, 370/466
• US Class Current: 370/465
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

Look ahead encoder and decoder architecture. To increase the encoding speed, bytes of input data to be encoded are applied in parallel to each encoder of a pair of encoders in the look ahead encoder architecture. One encoder of each pair receives a first control input signal, while the other receives a second control input signal. The output bytes of binary data from the two encoders are applied to a multiplexer which selects the proper output byte based on the control output signal resulting from the immediately preceding encoded output byte of binary data. In one embodiment, a single encoder encodes the previous byte, doubling the encoding speed. In a second embodiment, a number of encoder pairs are utilized, with the multiplexers connected in a ring to utilize the selected control output signal from one multiplexer as the select signal for the next multiplexer in the ring, increasing the encoder speed by a factor equal to the number of encoder pairs. The look ahead decoder archtecture is correspondingly structured. Data communication systems incorporating such encoder and decoder architecture are provided. The encoders might be 8-bit/10-bit encoders, with the decoders then being 8-bit/10-bit decoders.

Claims

1. An encoder network, comprising:

a plurality of pairs of encoders, each encoder capable of encoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to one encoder of each of said pairs of encoders;

a second control signal source providing a second control input signal to the other encoder of each of said pairs of encoders;

a data source providing successive input bytes of binary data cyclically to each encoder pair, for simultaneous encoding thereof by each encoder of such encoder pair;

a like plurality of multiplexers, each multiplexer multiplexing the output bytes and control output signals provided by the two encoders of an associated one of said plurality of pairs of encoders in accordance with a select control signal applied to a select input of such multiplexer, each multiplexer applying its control output signal as the select control signal of another of said multiplexers to connect said plurality of multiplexers in a ring; and

a delay circuit for delaying application of the control output signal of one of said multiplexers to the select input of the next multiplexer in the ring.

2. An encoder network as claimed in claim 1, wherein said delay circuit comprises a flip-flop.

3. An encoder network as claimed in claim 1, wherein each of said encoders is an 8bit/10-bit encoder.

4. An encoder network comprising:

first, second and third encoders, each encoder capable of encoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to said second encoder;

a second control signal source providing a second control input signal to said third encoder;

a data source providing successive bytes of binary data alternately to said first encoder, for encoding thereof by said first encoder, and in parallel to said second and third encoders, for simultaneous encoding thereof by said second and third encoders;

an output connection;

a selection circuit for selecting the binary data output bytes from one of said second and third encoders for application to said output-connection, based on the control output signal from said first encoder, and

a control circuit responsive to the control output signal from said first encoder for selecting one of the control output signal from said second encoder and the control output signal from said third encoder to provide the control input signal to said first encoder for use in encoding a subsequent byte of binary data.

5. An encoder network as claimed in claim 4, wherein said selection circuit comprises a multiplexer.

6. An encoder network as claimed in claim 4, wherein said control circuit comprises a multiplexer and a delay circuit.

7. An encoder network as claimed in claim 6, wherein said delay circuit comprises a flip-flop.

8. An encoder network as claimed in claim 4, wherein each encoder is an 8-bit/10-bit encoder.

9. A decoder network, comprising:

a plurality of pairs of decoders, each decoder capable of decoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to one decoder of each of said pairs of decoders;

a second control signal source providing a second control input signal to the other decoder of each of said pairs of decoders;

a data source providing successive input bytes of binary data cyclically to each decoder pair, for simultaneous decoding thereof by each decoder of such decoder pair;

a like plurality of multiplexers, each multiplexer multiplexing the output bytes and control output signals provided by the two decoders of an associated one of said plurality of pairs of decoders in accordance with a select control signal applied to a select input of such multiplexer each multiplexer applying its control output signal as the select control signal of another of said multiplexers to connect said plurality of multiplexers in a ring; and

a delay circuit for delaying application of the control output signal of one of said multiplexers to the select input of the next multiplexer in the ring.

10. A decoder network as claimed in claim 9, wherein said delay circuit comprises a flip-flop.

11. A decoder network as claimed in claim 9, wherein each decoder is an 8-bit/10-bit decoder.

12. A decoder network, comprising:

first, second and third decoders, each decoder capable of decoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to said second decoder,

a second control signal source providing a second control input signal to said third decoder;

a data source providing successive bytes of binary data alternately to said first decoder, for decoding thereof by said first decoder, and in parallel to said second and third decoders, for simultaneous decoding thereof by said second and third decoders;

an output connection;

a selection circuit for selecting the binary data output bytes from one of said second and third decoders for application to said output connection, based on the control output signal from said first decoder; and

a control circuit responsive to the control output signal from said first decoder for selecting one of the control output signal from said second decoder and the control output signal to said third decoder to provide a control input signal to said first decoder for use in decoding a subsequent byte of binary data.

13. A decoder network as claimed in claim 12, wherein said selection circuit comprises a multiplexer.

14. A decoder network as claimed in claim 12, wherein said control circuit comprises a multiplexer and a delay circuit.

15. A decoder network as claimed in claim 14, wherein said delay circuit comprises a flip-flop.

16. A decoder network as claimed in claim 12, wherein each decoder is an 8-bit/10-bit decoder.

17. A data communication system comprising:

first, second, and third encoders, each encoder capable encoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to said second encoder;

a second control signal source providing a second control input signal to said third encoder;

a data source providing successive bytes of binary data alternately to said first encoder, for encoding thereof by said first encoder, and in parallel to said second and third encoders, for simultaneous encoding thereof by said second and third encoders;

a first selection circuit for selecting the output byte from one of said second and third encoders based on the control output signal from said first encoder;

a first control circuit responsive to the control output signal from said first encoder for selecting one of the control output signal from said second encoder and the control output signal from said third encoder to provide a control input signal to said first encoder;

first, second, and third decoders, each decoder capable of decoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a third control signal source providing a third control input signal to said second decoder;

a fourth control signal source providing a fourth control input signal to said third decoder;

a transmission network coupling the output byte from said first encoder and the selected output byte from said second and third encoders to said first decoder and in parallel to said second and third decoders for decoding;

a second selection circuit for selecting the output byte from one of said second and third decoders based on the control output signal from said first decoder;

a second control circuit responsive to the control output signal from said first decoder for selecting one of the control output signal from said second decoder and the control output signal from said third decoder to provide a control input signal to said first decoder; and

a decoder output circuit for outputting the output byte from said first decoder and the selected output byte from said second and third decoders.

18. A data communication system as claimed in claim 17, wherein each of said first and second selection circuits comprises a multiplexer.

19. A data communication system as claimed in claim 17, wherein each of said control circuits comprises a multiplexer and a delay circuit.

20. A data communication system as claimed in claim 19, wherein said delay circuit comprises a flip-flop.

21. A data communication system as claimed in claim 17, wherein each of said encoders is an 8-bit/10-bit encoder, and each of said decoders is an 8-bit/10-bit decoder.

22. A data communication system, comprising:

a plurality of pairs of encoders, each encoder capable of encoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a first control signal source providing a first control input signal to one encoder of each of said pairs of encoders;

a second control signal source providing a second control input signal to the other encoder of each of said pairs of encoders;

a data source providing successive input bytes of binary data cyclically to each encoder pair, for simultaneous encoding thereof by each encoder of such encoder pair;

a like plurality of first multiplexers, each first multiplexer multiplexing the output bytes and control output signals provided by the two encoders of an associated one of said plurality of pairs of encoders in accordance with a select control signal applied to a select input of such multiplexer, each first multiplexer applying its control output signal as the select control signal of another of said first multiplexers to connect said plurality of first multiplexers in a ring,

a first delay circuit for delaying application of the control output signal of one of said first multiplexers to the select input of the next first multiplexer in the ring;

a plurality of pairs of decoders, each decoder capable of decoding an input byte of binary data based on a control input signal to provide a corresponding output byte of binary data and a control output signal;

a third control signal source providing a third control input signal to one decoder of each of said pairs of decoders;

a fourth control signal source providing a fourth control input signal to the other decoder of each of said pairs of decoders;

a transmission line for applying the encoded data byte outputs of said plurality of first multiplexers as input bytes to said plurality of pairs of decoders;

a like plurality of second multiplexers, each second multiplexer multiplexing the output bytes and control output signals provided by the two decoders of an associated one of said plurality of pairs of decoders in accordance with a select control signal applied to a select input of such multiplexer, each second multiplexer applying its control output signal as the select control signal of another of said second multiplexers to connect said plurality of second multiplexers in a ring;

a second delay circuit for delaying application of the control output signal of one of said second multiplexers to the select input of the next one of said second multiplexers in the ring; and

a decoder output circuit for outputting the decoded data byte outputs of said second plurality of multiplexers.

23. A data communication system as claimed in claim 22, wherein each of said encoders is an 8-bit/10-bit encoder, and each of said decoders is an 8-bit/10-bit decoder.