Area-optimum rapid acquisition cellular multi-protocol digital DC offset correction scheme

• US 6,606,359 B1
• Filed: 07/26/2000
• Issued: 08/12/2003
• Est. Priority Date: 07/26/2000
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Nag, Manbir, Mittel, James
• Primary Examiner(s): Ghayour, Mohammad H.
• Assistant Examiner(s): AL BESHRAWI, TONY
• Application Number:
  US09/626,466
• Time in Patent Office: 1,112 Days
• Field of Search: 375/348, 375/319, 455/296
• US Class Current: 375/348
• CPC Class Codes: H03F 1/304 and using digital means
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03K 5/003 Changing the DC level reinsertion of dc component of a television signal H04N5/16
• CPC Class Codes: H04L 25/064 Subtraction of the threshold from the signal, which is then compared to a supplementary fixed threshold

Abstract

A digital DC offset correction circuit (68) provides DC offset correction within a receiver (50) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit (68) includes an integrator (90), a low pass filter (92), a decimator (94), a digital to analog converter codeword clamp (96), and a digital to analog converter (98).

Claims

1. A receiver for receiving and processing a radio frequency signal using an area-optimum rapid acquisition cellular multi-protocol digital dc offset correction scheme within a radio communication system, the receiver comprising:

a receiver antenna for receiving the radio frequency signal;

a radio frequency frontend coupled to the receiver antenna for receiving the radio frequency signal and for generating a desired signal;

a post mixer amplifier coupled to the radio frequency frontend receiving the desired signal and for generating a post mixer amplifier output;

a first anti-alias filter coupled to the post mixer amplifier for generating a first anti-alias filter output;

a summing junction coupled to the first anti-alias filter for receiving the first anti-alias filter output and an offset correction signal and for generating a combined intermediate frequency signal;

an intermediate frequency amplifier circuit coupled to the summing junction for receiving the combined intermediate frequency signal and for generating an intermediate frequency amplifier output;

a second anti-alias filter coupled to the intermediate frequency amplifier circuit receiving the intermediate frequency amplifier output and for generating a second anti-alias filter output;

an analog to digital converter coupled to the second anti-alias filter for receiving the second anti-alias filter output and for generating a most significant bit and a least significant bit; and

a digital DC offset correction circuit coupled between the analog to digital converter and the summing junction, for receiving the least significant bit and for generating the offset correction signal.

2. A receiver for receiving and processing a radio frequency signal as recited in claim 1, wherein the analog to digital converter comprises a second order noise-shaping sigma-delta analog to digital converter.

3. A digital DC offset correction circuit for providing DC offset correction within a receiver for receiving and processing a radio frequency signal using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme within a radio communication system, the receiver including an analog to digital converter and a clock, the digital DC offset correction circuit comprising:

an integrator, for receiving a least significant bit from the analog to digital converter and for generating an integrator output;

a low pass filter coupled to the integrator for receiving the integrator output and for generating a low pass filter output;

a decimator coupled to the low pass filter for receiving the low pass filter output and for generating a decimator output;

a digital to analog converter codeword clamp coupled to the decimator for receiving the decimator output and for generating a clamped signal; and

a digital to analog converter coupled to the digital to analog converter codeword clamp for receiving the clamped signal and for generating an offset correction signal.

4. A digital DC offset correction circuit as recited in claim 3, wherein the integrator comprises:

an integrator summing junction for receiving the least significant bit and the integrator output, wherein the integrator summing junction combines the least significant bit and the integrator output, thereby generating an integrator summing junction output; and

an integrator flip-flop coupled to the integrator summing junction for receiving the integrator summing junction output and the clock, wherein the integrator flip-flop delays the integrator summing junction output for one clock cycle, thereby generating the integrator output.

5. A digital DC offset correction circuit as recited in claim 3, wherein the low pass filter comprises:

a first filter summing junction for receiving the integrator output and a first filter amplifier output, wherein the first filter summing junction combines the integrator output and the first filter amplifier output, thereby generating a first filter summing junction output;

a filter flip-flop, coupled to the first filter summing junction, for receiving the first filter summing junction output and for receiving the clock, wherein the filter flip-flop delays the first filter summing junction output by one clock cycle, thereby generating a filter flip-flop output;

a first filter amplifier, coupled between the filter flip-flop and the first filter summing junction, for receiving the filter flip-flop output, wherein the first filter amplifier provides gain to the filter flip-flop output, thereby generating a first filter amplifier output;

a second filter summing junction, coupled to the filter flip-flop and coupled to the first filter summing junction, for receiving the first filter summing junction output and the filter flip-flop output, wherein the second filter summing junction combines the first filter summing junction output and the filter flip-flop output, thereby generating a second filter summing junction output; and

a second filter amplifier, coupled to the second filter summing junction, for receiving the second filter summing junction output, wherein the second filter amplifier provides gain to the second filter summing junction output, thereby generating the low pass filter output.

6. A digital DC offset correction circuit as recited in claim 3, wherein the low pass filter comprises an infinite impulse response circuit.

7. A digital DC offset correction circuit as recited in claim 3, wherein the decimator comprises:

a decimator flip-flop, wherein the decimator flip-flop receives the low pass filter output and the clock and further wherein the decimator flip-flop delays the low pass filter output by one clock cycle, thereby generating the decimator output.

8. A digital DC offset correction circuit as recited in claim 3, wherein the digital to analog converter codeword clamp comprises:

an operational amplifier, wherein the operational amplifier functions in a unity gain mode.

9. A digital DC offset correction circuit as recited in claim 3, wherein the digital to analog converter comprises:

a voltage controlled current source for receiving the clamped signal and the clock and for generating the offset correction signal; and

a load resistor coupled to the output of the voltage controlled current source.