Method and apparatus for receiving data

• US 6,606,360 B1
• Filed: 12/30/1999
• Issued: 08/12/2003
• Est. Priority Date: 12/30/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dunning, David S., Abhayagunawardhana, Chamath
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/475,505
• Time in Patent Office: 1,321 Days
• Field of Search: 375/354, 375/369, 375/370, 375/371, 375/373, 375/375, 375/376, 375/316, 375/327, 375/215, 375/226, 375/326, 375/279, 375/329, 327/3, 327/12, 327/24, 327/26, 327/27, 327/156, 327/171, 370/503, 329/307, 329/325, 329/360, 331/1.R, 331/25
• US Class Current: 375/354
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A method and apparatus for asynchronously receiving a stream of data. The method and apparatus operate to detect edges within the stream of data and track a transmitted clock using multiple locally-generated clock phases. Moreover, the method and apparatus determine whether each edge arrives early or late relative to an expected arrival time and use the determination whether an edge arrived early or late in a receiver decision process. An exemplary embodiment of the apparatus to recover a clock from a stream of data includes an edge buffer, an edge processor, a multi-phase clock and an elastic buffer. The edge buffer receives the data stream and outputs an edge signal that indicates detection of an edge within the data stream. The edge processor is coupled to the edge buffer, determines an average phase of the detected edges and outputs a data signal and the average phase. The multi-phase clock is coupled to the edge processor, and outputs a multiple clock phases offset from each other by a predetermined amount. The elastic buffer is coupled to the edge processor and the multi-phase clock and outputs the data and the average phase.

Claims

1. A method to asynchronously receive a stream of data comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process; and

incrementing a count in a counter, one counter for each of the plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges base on the counter in the counter.

2. The method according to claim 1, further comprising calculating a moving average of the plurality of edges.

3. The method according to claim 2, further comprising using the moving average to determine the expected arrival time.

4. The method according to claim 1, further comprising placing the plurality of detected edges in an asynchronous pipeline and clocking the detected edges out into an edge processor using a locally-generated clock.

5. The method according to claim 1, further comprising synchronizing the plurality of edges to the plurality of locally-generated clock phases.

6. The method according to claim 1, further comprising generating the plurality of locally-generated clock phases at a receiving end.

7. The method according to claim 1, further comprising qualifying the plurality of detected edges for use in subsequent processing using historical information.

8. A method to asynchronously receive a stream of data comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process;

qualifying the plurality of detected edges for use in subsequent processing using historical information; and

incrementing a count in a counter, one counter for each of the plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

9. A method to asynchronously receive a stream of data comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process;

qualifying the plurality of detected edges for use in subsequent processing using historical information; and

assigning a counter for each of the plurality of locally-generated clock phases, incrementing a particular counter associated with a particular clock phase each time a qualified detected edge is closest in time to said particular clock phase and determining a moving average phase of the qualified detected edges based on values in the counter.

10. A method to asynchronously receive a stream of data comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process;

qualifying the plurality of detected edges for use in subsequent processing using historical information; and

assigning a counter for each of the plurality of locally-generated clock phases, incrementing a particular counter associated with a particular clock phase each time a qualified detected edge is closest in time to said particular clock phase, said selecting one of the plurality of locally-generated clock phases whose assigned counter is a maximum as a moving average phase of the qualified detected edges.

11. An apparatus to recover a clock from a stream of data comprising:

a) an edge buffer to receive the data stream and output an edge signal that indicates detection of a plurality of edges within the data stream;

b) an edge processor coupled to the edge buffer to determine an average phase of the detected edges and output a data signal and the average phase;

c) a multi-phase clock coupled to the edge processor to output a plurality of clock phases offset from each other by a predetermined amount; and

d) an elastic buffer coupled to the edge processor and the multi-phase clock to output the data and the average phase.

12. The apparatus according to claim 11, wherein the edge buffer comprises:

a) an edge detector to detect edges in the data stream; and

b) an edge pipeline coupled to the edge detector to temporarily store the detected edges.

13. The apparatus according to claim 11, wherein the edge detector comprises a high-gain, high-bandwidth comparator to amplify minimum input signal swings to levels detectable by CMOS logic.

14. The apparatus according to claim 11, wherein the edge buffer further comprises an edge pipeline into which detected edges are temporarily stored and clocked out by the edge processor.

15. The apparatus according to claim 11, wherein the edge processor comprises a synchronizer to compare an edge signal to the plurality of locally-generated clock phases, select a clock phase among the plurality of locally-generated clock phases closest to the edge signal and output a phase voting signal to indicate which clock phase was closest to each edge signal.

16. The apparatus according to claim 15, wherein the edge processor further comprises a phase picking logic circuit coupled to the synchronizer to determine the average phase based on the phase voting signal received from the synchronizer.

17. The apparatus according to claim 16, wherein the phase picking logic circuit further comprises:

a) an edge qualifier to receive the phase voting signal and select qualified voting signals among the phase voting signals based on historical data regarding the received data stream;

b) a plurality of counters to count the phase voting signals, one for each of the plurality of clock phases; and

c) maximizer to determine which one of the plurality of counters is maximum and output the clock phase associated with said one of the plurality of counters that is a maximum as the average phase.

18. An asynchronous receiving method to receive a data stream in a received waveform comprising:

detecting a plurality of edges of the received waveform;

using a local clock to determine an average phase of the plurality of edges of the received waveform;

predicting a time when a next edge should be received based on the calculated average and determining whether the next edge was received early or late relative to the predicted time; and

incrementing a count in a counter, one counter for each of a plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

19. The method according to claim 18, further comprising making a decision as to a received symbol using the determination whether the next edge was received early or late relative to the predicted time.

20. An apparatus to recover a clock from a stream of data encoded as a positive differential signal and a negative differential signal, comprising:

a) an edge buffer to receive the positive and negative differential signals and output a positive zero crossing signal to indicate an occurrence of a rising edge of the positive differential signal and a negative zero crossing signal to indicate an occurrence of a rising edge of the negative differential signal;

b) an edge processor coupled to the edge buffer to determine an average phase of the positive and negative zero crossing signals and output a data signal and the average phase; and

c) a multi-phase clock coupled to the edge processor to output a plurality of clock phases offset from each other by a predetermined amount.

21. The apparatus according to claim 20, further comprising an elastic buffer coupled to the edge processor and the multi-phase clock to output the data and the average phase.

22. The apparatus according to claim 20, wherein the edge buffer comprises:

a) an edge detector to detect the positive and negative zero crossings;

b) a positive asynchronous pipeline coupled to the edge detector to temporarily store the positive zero crossings; and

c) a negative asynchronous pipeline coupled to the edge detector to temporarily store the negative zero crossings.

23. The apparatus according to claim 20, wherein the edge detector comprises a high-gain, high-bandwidth comparator to amplify minimum input signal swings to levels detectable by CMOS logic.

24. The apparatus according to claim 20, wherein the edge processor comprises:

a) a positive synchronizer to compare the positive zero crossings to the plurality of locally-generated clock phases, select a clock phase among the plurality of locally-generated clock phases that lies closest in time to each of the positive zero crossings and output a positive phase voting signal to indicate which clock phase was closest to each of the positive zero crossings; and

b) a negative synchronizer to compare the negative zero crossings to the plurality of locally-generated clock phases, select a clock phase among the plurality of locally-generated clock phases that lies closest in time to the each of the negative zero crossings and output a negative phase voting signal to indicate which clock phase was closest to each of the negative zero crossings.

25. The apparatus according to claim 24, wherein the edge processor further comprises a phase picking logic circuit coupled to the positive and negative synchronizers to determine an average phase based on the positive and negative phase voting signals received from the positive and negative synchronizers.

26. The apparatus according to claim 25, wherein the phase picking logic circuit further comprises:

a) an edge qualifier to receive the positive and negative phase voting signals and select qualified voting signals among the positive and negative phase voting signals based on historical data regarding the received data stream;

b) a plurality of counters to count the positive and negative phase voting signals, one for each of the plurality of clock phases; and

c) a maximizer to determine which one of the plurality of counters is maximum and output the clock phase associated with said one of the plurality of counters that is a maximum as the average phase.

27. A computer system including a plurality of modular components communicating with each other, each of the modular components employing an asynchronous receiving method to receive a data stream from another modular component, said asynchronous receiving method comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process; and

incrementing a count in a counter, one counter for each of the plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

28. A communications system including a plurality of components communicating with each other, each of the components employing an asynchronous receiving method to receive a data stream from another component, said asynchronous receiving method comprising:

detecting a plurality of edges within the stream of data;

tracking a transmitted clock with a plurality of locally-generated clock phases;

determining whether each edge arrives early or late relative to an expected arrival time;

using the determination whether an edge arrived early or late in a receiver decision process; and

incrementing a count in a counter, one counter for each of the plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

29. A method to receive a stream of data comprising:

detecting a plurality of edges within the stream of data;

generating a plurality of locally-generated clock phases;

tracking at least some of the edges with the locally-generated clock phases;

selecting one of the plurality of locally-generated clock phases based upon the tracking; and

incrementing a count in a counter, one counter for each of the plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

30. An asynchronous receiving method to receive a data stream in a received waveform comprising:

detecting a plurality of edges of the received waveform;

using a local clock to determine an average phase the plurality of edges of the received waveform; and

incrementing a count in a counter, one counter for each of a plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.

31. An asynchronous receiving method to receive a data stream in a received waveform comprising:

detecting a plurality of edges of the received waveform;

outputting a data stream based upon the detected plurality of edges; and

incrementing a count in a counter, one counter for each of a plurality of locally-generated clock phases, every time a qualified detected edge is closest to one of the plurality of locally-generated clock phases and determining an average phase of the qualified detected edges based on the counts in the counter.