Cross-correlation timing calibration for wafer-level IC tester interconnect systems

• US 6,606,575 B2
• Filed: 12/29/2000
• Issued: 08/12/2003
• Est. Priority Date: 06/20/2000
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): Sun, Xiuqin
• Application Number:
  US09/752,839
• Publication Number:
  US 20020049554A1
• Time in Patent Office: 956 Days
• Field of Search: 324/754, 324/751, 714/814, 380/218, 327/538, 360/53
• US Class Current: 702/104
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3191 Calibration

Abstract

To calibrate timing of test signals generated by all channels of an integrated circuit, each channel is programmed to generate a test signal having a repetitive pseudo-random test signal edge pattern. The test signal pattern of each channel is compared to a reference signal having the same edge pattern and the delay of each channel is adjusted to maximize cross-correlation between the test signal and the reference signal.

Claims

1. A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel:

a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel'"'"'s corresponding probe tip,

b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal,

c. generating a periodic reference (REF) signal having said repetitive edge timing pattern, and

d. cross-correlating the TEST signal generated at step b to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.

2. The method in accordance with claim 1 further comprising the steps of for each said tester channel:

e. performing a plurality of iterations of steps b-d, providing the tester channel with differing values of the input drive calibration data during each iteration of step b; and

f. determining a particular iteration of steps b-d for which cross-correlation data produced at step d indicates the channel'"'"'s TEST signal most closely matched the REF signal in phase.

3. The method in accordance with claim 2 further comprising for each said tester channel the step of:

g. calibrating timing of the tester channel by providing input drive calibration data to said tester channel of value matching that of input drive calibration data provided to said tester channel during said particular iteration of steps b-d determined at step f.

4. The method in accordance with claim 3 wherein step d comprises the substeps of:

d1. generating a MATCH signal having a magnitude indicating how well an amplitude of the periodic TEST signal appearing at the probe tip matches an amplitude of the REF signal,

d2. integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal, and

d3. digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data.

5. The method in accordance with claim 4 wherein said successive edges of said TEST signal within said repetitive edge timing pattern are separated by non-uniform intervals.

6. The method in accordance with claim 4 wherein successive edges of the TEST signal within said repetitive edge timing pattern are separated by intervals of pseudo-random duration.

7. The method in accordance with claim 3 wherein said successive edges of said TEST signal within said repetitive edge timing pattern are separated by non-uniform intervals.

8. The method in accordance with claim 3 wherein successive edges of the TEST signal edges within said repetitive edge timing pattern are separated by intervals of pseudo-random duration.

9. The method in accordance with claim 2 wherein step d comprises the substeps of:

d1. generating a MATCH signal having a magnitude indicating how well an amplitude of the periodic TEST signal appearing at the probe tip matches an amplitude of the REF signal,

d2. integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal, and

d3. digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data.

10. The method in accordance with claim 1 wherein step d comprises the substeps of:

d1. generating a MATCH signal having a magnitude indicating how closely the TEST signal and the REF signal match in amplitude, and

d2. generating the cross-correlation data representing an integral of the MATCH signal over a finite time interval.

11. The method in accordance with claim 10 wherein substep d2 comprises the further substeps of:

integrating the MATCH signal over said finite time interval to produce an analog cross-correlation (CC) signal, and

digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data.

12. The method in accordance with claim 1 wherein said successive edges of said TEST signal within said repetitive edge timing pattern are separated by non-uniform intervals.

13. The method in accordance with claim 1 wherein successive edges of the TEST signal edges within said repetitive edge timing pattern are separated by intervals of pseudo-random duration.

14. A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel:

a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel'"'"'s corresponding probe tip;

b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal;

c. generating a periodic reference (REF) signal having said repetitive edge timing pattern;

d. generating a MATCH signal having a magnitude indicating how well an amplitude of the periodic TEST signal appearing at the probe tip matches an amplitude of the REF signal;

e. integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal;

f. digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data;

g. performing a plurality of iterations of steps b-f, providing the tester channel with differing values of the input drive calibration data during each iteration of step b;

h. determining a particular iteration of steps b-f for which cross-correlation data produced at step f indicates the channel'"'"'s TEST signal most closely matched the REF signal in phase; and

i. calibrating timing of the tester channel by providing input drive calibration data to said tester channel of value matching a that of input drive calibration data provided to said tester channel during said particular iteration of steps b-f determined at step h.

15. The method in accordance with claim 14 wherein said successive edges of said TEST signal within said repetitive edge timing pattern are separated by non-uniform intervals.

16. The method in accordance with claim 14 wherein successive edges of the TEST signal edges within said repetitive edge timing pattern are separated by intervals of pseudo-random duration.

17. The method in accordance with claim 14 wherein successive edges of the TEST signal edges within said repetitive edge timing pattern are separated by intervals of uniform duration.

18. An apparatus for testing an integrated circuit (IC) having a plurality of input/output (I/O) terminals, the apparatus comprising:

means for generating a periodic CLOCK signal;

a plurality of probes with tips, each for contacting a separate I/O terminal of said IC

a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel;

means for generating a reference (REF) signal having a repetitive edge timing pattern; and

cross-correlation means for cross-correlating the TEST signal generated at each probe tip to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.

19. The apparatus in accordance with claim 18 further comprising:

control means for supplying programming data supplied to each of said tester channel causing each tester channel to produce its TEST signal at its corresponding probe tip with an edge timing pattern similar to that of the REF signal, and for iteratively altering the drive calibration data input to each channel and monitoring the cross-correlation data produced by said cross-correlation means to determine for each tester channel a value of said drive calibration data for which said cross-correlation data indicates the TEST signal most closely matches the REF signal in phase.

20. The apparatus in accordance with claim 19 wherein said cross-correlation means comprises:

means for generating a MATCH signal having a magnitude indicating how well an amplitude of each of the TEST signals appearing at said probe tips matches an amplitude of the REF signal;

means for integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal, and

means for digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data.

21. The apparatus in accordance with claim 20 wherein the means for generating the MATCH signal comprises an exclusive OR gate.

22. The apparatus in accordance with claim 20 wherein the means for generating the MATCH signal comprises an analog multiplier circuit.