Design apparatus and a method for generating an implementable description of a digital system

• US 6,606,588 B1
• Filed: 01/26/1999
• Issued: 08/12/2003
• Est. Priority Date: 03/14/1997
• Status: Expired due to Fees

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Vernalde, Serge, Cockx, Johan, Schaumont, Patrick
• Primary Examiner(s): Frejd, Russell
• Application Number:
  US09/237,549
• Time in Patent Office: 1,659 Days
• Field of Search: 703/13, 703/23, 703/27, 703/20, 703/14, 703/15, 716/7, 716/3, 716/18, 716/5, 716/8, 716/11, 716/6, 716/12, 717/104, 717/108, 717/114, 717/116
• US Class Current: 703/15
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Claims

1. A design apparatus for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for the system, the behavioral description being represented on the computer environment as a first set of objects with a first set of relations therebetween, the implementable description being represented on the computer environment as a second set of objects with a second set of relations therebetween, the first and second set of objects being part of a design environment.

2. The design apparatus of claim 1 wherein the first and second set of objects are part of a single design environment.

3. The design apparatus of claim 1, wherein the design environment comprises an Object Oriented Programming Language.

4. The design apparatus of claim 3, wherein the Object Oriented Programming Language is C++.

5. The design apparatus of claim 1, wherein the design environment is an open environment wherein new objects are created.

6. The design apparatus of claim 1, wherein at least part of the input signals and output signals of the first set of objects are at least part of the input signals and output signals of the second set of objects.

7. The design apparatus of claim 6, wherein at least part of the input signals and output signals of the behavioral description are at least part of the input signals and output signals of the implementable description.

8. The design apparatus of claim 1, wherein the first set of objects has first semantics and the second set of objects has second semantics.

9. The design apparatus of claim 8, wherein the first semantics is a data-vector model and/or a data-flow model.

10. The design apparatus of claim 8, wherein the second semantics is a signal flow graph (SFG) data structure.

11. The design apparatus of claim 1, wherein the impact in the implementable description of at least a part of the objects of the second set of objects is essentially the same as the impact in the behavioral description of at least a part of the objects of the first set of objects.

12. The design apparatus of claim 1, further comprising means for simulating the behavior of the system, the means simulating the behavior of the behavioral description, the implementable description or any intermediate description therebetween.

13. The design apparatus of claim 1, wherein at least part of the second set of objects is derived from objects belonging to the first set of objects.

14. The design apparatus of claim 1, wherein the implementable description is at least partly obtained by refining the behavioral description.

15. The design apparatus of claim 1, wherein the implementable description is an architecture description of the system.

16. The design apparatus of claim 15, further comprising means for translating the architecture description into a synthesizable description of the system, the synthesizable description being directly implementable in hardware.

17. The design apparatus of claim 16, wherein the hardware is a semiconductor chip.

18. The design apparatus of claim 1, further comprising means to derive the first set of objects from a vector description describing the system as a set of operations on data vectors.

19. The design apparatus of claim 18, wherein the vector description is a MATLAB description.

20. The design apparatus of claim 9, further comprising means for simulating statically or demand-driven scheduled dataflow on the data-flow description.

21. The design apparatus of claim 1, further comprising means for clock-cycle true simulating the digital system using a data-flow description and/or one or more of SFG data structures using an expectation-based simulation.

22. The design apparatus as recited in claim 1, wherein said objects comprise a function.

28. The method of claim 22, wherein the data-flow model is an untimed floating point data-flow model.

29. The method of claim 22, wherein refining further comprises a second refining wherein the data-flow model is at least partly transformed into an SFG model.

31. The method of claim 29, wherein determining the amount of parallelism comprises determining the amount of parallelism for every data vector and reducing the unspecified communication bandwidth of the data-vector model to a fixed number of communication buses in the data-flow model.

32. The method of claim 29, wherein determining actors, edges and tokens of the behavioral description comprises defining one or a group of data vectors in the first data-vector model as actors;

defining data precedences crossing actor bounds, as edges, the edges behaving like queues and transporting tokens between actors; and

constructing a system schedule and running a simulation on a computer environment.

35. The method of claim 29, further comprising combining several of the SFG models with a finite state machine description resulting in an implementable description.

36. The method of claim 35, further comprising transforming the implementable description to synthesizable code.

37. The method of claim 36, wherein the synthesizable code is VHDL code.

41. A hardware circuit or a software simulation of a hardware circuit designed with the design apparatus of claim 1.

23. A method of designing a system comprising at least one digital part, the method comprising refining wherein a behavioral description of the system is transformed into an implementable description of the system, the behavioral description being represented as a first set of objects with a first set of relations therebetween and the implementable description being represented as a second set of objects with a second set of relations therebetween, wherein refining comprises a first refining wherein the behavioral description is a data-vector model and is at least partly transformed into a data-flow model.

24. The method of claim 23, wherein refining comprises translating behavioral characteristics at least partly into structural characteristics.

25. The method of claim 23, further comprising simulating the behavior of the behavioral description, wherein the implementable description and/or any intermediate description therebetween is simulated.

26. The method of claim 23, wherein refining comprises adding new objects, permitting interaction with existing objects, and adjusting existing objects allowing the interaction.

27. The method of claim 23, wherein refining is performed in an open environment and comprises expansion of existing objects.

30. The method of claim 23, wherein refining comprises a first refining comprising:

determining the input vector lengths of input, output and intermediate signals;

determining the amount of parallelism of operations that process input signals to output signals;

determining actors, edges and tokens of the behavioral description; and

determining the wordlength of the tokens.

33. The method of claim 23, wherein the second set of objects with the second set of relations therebetween are at least partly derived from the first set of objects with the first set of relations therebetween.

34. The method of claim 23, wherein objects belonging to the second set of objects are new objects, identical with and/or derived by inheritance from objects from the first set of objects, or a combination thereof.

42. A hardware circuit or a software simulation of a hardware circuit designed with the method of claim 23.

43. The method as recited in claim 23, wherein said objects comprise a function.

44. The method as recited in claim 27, wherein said expansion includes the addition of functions to an existing object for creating a new object.

45. The method of claim 44, wherein the implementable description is automatically transformable.

38. A method of simulating a system, the method comprising transforming a description of a system into compilable C++ code that is suitable for simulating the system as software, wherein the description is an implementable description, wherein the implementable description is transformable into synthesizable code.

39. The method of claim 38, wherein the description is an SFG data structure and the compilable C++ code is used to perform clock-cycle true simulations.

40. A method of simulating a system, wherein a description of a system is transformed into compilable C++ code, wherein the description comprises the combination of several SFG data structures with a finite state machine description resulting in an implementable description, the implementable description being the compilable C++ code suitable for simulating the system as software.